Is there a relationship between the speed of the front side bus and the speed of the CPU? Does the CPU speed have to be a multiple of the CPU speed?
multipier x FSB = processor speed.
FSB is the basic frequency on the motherboard and all the other are derived from it. the PCI bus is derived from the FSB by a divider usually 4 giving a PCI speed of 33.3 MHz, which is further divided by a factor of say 4 to give the ISA clock which is 8.33 MHz.
With FSBs getting higher than 133 MHz you need a higher divider of 5 so that the PCI bus stays at around 33. Other devices might not complain but it is the IDE controller that is on the PCI bus that locks up.
AGP clock is also derived from the FSB to be 66 MHz.
Change in FSB also affects these clocks proportionally and that is why overclocking has limitations not directly related to the processor itself.
<font color=red>No system is fool-proof. Fools are Ingenious!</font color=red>
FSB is the basic frequency on the motherboard and all the other are derived from it. the PCI bus is derived from the FSB by a divider usually 4 giving a PCI speed of 33.3 MHz, which is further divided by a factor of say 4 to give the ISA clock which is 8.33 MHz.
With FSBs getting higher than 133 MHz you need a higher divider of 5 so that the PCI bus stays at around 33. Other devices might not complain but it is the IDE controller that is on the PCI bus that locks up.
AGP clock is also derived from the FSB to be 66 MHz.
Change in FSB also affects these clocks proportionally and that is why overclocking has limitations not directly related to the processor itself.
<font color=red>No system is fool-proof. Fools are Ingenious!</font color=red>
- Dec 31, 2007
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LOL, actually I apreciate it when others answer some of these questions well, as there are so many out there trying to push the wrong information that it's hard for me to keep up. Your taking some of my load off, thanks!
Back to you Tom...
Back to you Tom...
actually no your wrong Ncogneto.
Take for instance AMD Thunderbird 1333 MHz. It is 133 x 10 = 1333, not 266 x 5.
Then look at Pentium 4 1800 MHz. It is 100 x 18 = 1800, not 4.5 x 400.
Double Pumped or Quad pumping is done insternally, and this is where my knowledge doesn't fully go. My guess is it just processes data more often "theoretically" giving more bandwidth. I know DDR front side bus processes data on the rising and falling edge of the clock cycle or something like that. Hopefully crashman will return and enlighten us all.
Take for instance AMD Thunderbird 1333 MHz. It is 133 x 10 = 1333, not 266 x 5.
Then look at Pentium 4 1800 MHz. It is 100 x 18 = 1800, not 4.5 x 400.
Double Pumped or Quad pumping is done insternally, and this is where my knowledge doesn't fully go. My guess is it just processes data more often "theoretically" giving more bandwidth. I know DDR front side bus processes data on the rising and falling edge of the clock cycle or something like that. Hopefully crashman will return and enlighten us all.
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Double pumping or quad pumping just refers to how often data is written to or read from memory per clock. Double or quad pumping results in a higher MB/s transfer, which equals higher bandwidth.
I agree that the numbers are confusing. That's why you see the occasional post about "My fsb only runs at 133, not 266"! No, it just <i>acts like</i> 266!
I feel really sorry for the poor shmoes who are buying these P4 systems with SDR SDRAM! What a ripoff! They don't understand that their powerful processor is being castrated by having a 100mhz fsb. [shakes head][thinks about quad pumped RDRAM, drools]
I agree that the numbers are confusing. That's why you see the occasional post about "My fsb only runs at 133, not 266"! No, it just <i>acts like</i> 266!
I feel really sorry for the poor shmoes who are buying these P4 systems with SDR SDRAM! What a ripoff! They don't understand that their powerful processor is being castrated by having a 100mhz fsb. [shakes head][thinks about quad pumped RDRAM, drools]
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actually it is seen by the cpu as 266 ( sytembus) x 5
Another Cookie? Who is going to pay my dentist bill?
So then does the p4 have a multiplier of 20?
100 x 20 = 2 gig? Actually we both may be correct. but the CPU see's a multiplier of x and then internally /2 in the case the the athlon or /4 in the case of the p4. These adjustments are done from within the processor, but nowadays so are the multipliers themselves.
So it can be argued either way which is more technically correct. But it will cause some confusion to a user that first thinks cpu speed equals fsb X multiplier, then finds out the fsb is double or quad pumped.
Another Cookie? Who is going to pay my dentist bill?<P ID="edit"><FONT SIZE=-1><EM>Edited by Ncogneto on 11/08/01 01:14 PM.</EM></FONT></P>
100 x 20 = 2 gig? Actually we both may be correct. but the CPU see's a multiplier of x and then internally /2 in the case the the athlon or /4 in the case of the p4. These adjustments are done from within the processor, but nowadays so are the multipliers themselves.
So it can be argued either way which is more technically correct. But it will cause some confusion to a user that first thinks cpu speed equals fsb X multiplier, then finds out the fsb is double or quad pumped.
Another Cookie? Who is going to pay my dentist bill?<P ID="edit"><FONT SIZE=-1><EM>Edited by Ncogneto on 11/08/01 01:14 PM.</EM></FONT></P>
I'm a bit confused.
What differance does the FSB really make?
We say that a p4 1700Mhz has an FSB frequency of 100MHz.
The "system bus" of the p4 is 400MHz (quad-pumped). This is used to communicate with the North bridge. The AGP talks to the memory controller at 4x66 Mhz, the memory talks to the MC at 400MHz with data coming at 800Mhz on a bus whose width is half that of the FSB, the south bridge communicates with the north bridge at a frequency not know to me, where the pci-bus operates at 33MHz et.c, et.c.
What component operates at the raw FSB-speed? Would a p4 system with a double pumped FSB @ 200MHz differ in any way from the present setup?
Why not use a 400MHz fsb in the first place?
What differance does the FSB really make?
We say that a p4 1700Mhz has an FSB frequency of 100MHz.
The "system bus" of the p4 is 400MHz (quad-pumped). This is used to communicate with the North bridge. The AGP talks to the memory controller at 4x66 Mhz, the memory talks to the MC at 400MHz with data coming at 800Mhz on a bus whose width is half that of the FSB, the south bridge communicates with the north bridge at a frequency not know to me, where the pci-bus operates at 33MHz et.c, et.c.
What component operates at the raw FSB-speed? Would a p4 system with a double pumped FSB @ 200MHz differ in any way from the present setup?
Why not use a 400MHz fsb in the first place?
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