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Intel's Breakthrough in Chip Transistor Design

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November 26, 2001 8:38:53 PM

Read the press release <A HREF="http://www.intel.com/pressroom/archive/releases/2001112..." target="_new">here</A>. I will go into more technical detail below. (Below is not the press release. It contains information adapted from a backgrounder paper. Follow the above link if you want to read the release.) Feel free to comment and discuss intelligently.

<b>Intel's TeraHertz Transistor Architecture</b>:

Intel’s researchers have developed a new type of transistor that it plans to use to make microprocessors and other logic products (such as chip sets) in the second half of the decade. The so-called "TeraHertz" transistors will allow the continuation of Moore’s Law, with the number of transistors doubling every 18 months, each one capable of running at multi-TeraHertz speeds, by solving the power consumption issue.

Intel has shown that it can scale transistors from 30nm (December 2000) to 20nm (June 2001), and to 15nm (November 2001). A transistor that scales in size by 30% is reduced in area by 50%, thus doubling the number of transistors, and thereby delivering more value to the end user by delivering applications that were previously not possible. It is also able to switch much faster. A TeraHertz transistor is able to switch between its "on" and "off" state over 1,000,000,000,000 times per second (equal to 1000 GigaHertz.)

The key problem solved by the TeraHertz transistor is that of power. As more and more transistors are packed onto a sliver of silicon, and they are run at higher and higher speeds, the total amount of power consumed by chips is getting out of hand. Chips that draw too much power get too hot, drain batteries unnecessarily (in mobile applications) and consume too much electricity. The latter is a particular problem in servers. If this power problem is not addressed, Moore’s Law will be throttled and futuristic applications such as real-time speech recognition and translation, real-time facial recognition (for security applications) or rendered graphics with the qualities of video will never be realized. These types of applications will require microprocessors with far more transistors than today, and running at much higher speeds than today.

The basic transistor in use today has 3 terminals: gate, source and drain. The transistor is an on/off switch. Electricity flows from source to drain if the gate is on; it does not flow if the gate is off (the gate’s state is determined by its voltage). The transistor is built on a wafer of silicon. The source and drain are variants of the basic silicon and the gate is a material called polysilicon. Below the gate is a thin layer called the gate dielectric. It is made of silicon dioxide today. All CMOS circuits today are made of transistors such as this, hooked up to each other by interconnects (wires). The Pentium 4 processor has 42 million such transistors on a fingernail-sized piece of silicon.

As mentioned previously, simply making these transistors smaller and faster is not feasible due to the power problem. Intel’s new TeraHertz transistor allows for scaling, and addresses the power problem. The goal with the TeraHertz transistor is that microprocessors will consume no more power than today, even though they will consist of many more transistors.

The TeraHertz transistor has 3 new features: a new gate dielectric, a layer of oxide buried within the silicon, and raised source and drain. These 3 features solve the power problem as follows:

<b>Problem 1</b>: Unwanted current flow across gate dielectric
<b>Why this is a problem</b>: As gate dielectrics get ever thinner, current leaks through, even though the dielectric is an insulator. This leads to a non-functioning, or improperly-functioning transistor.

<b>New solution</b>: Replace silicon dioxide with a new material with a "high k" value
<b>How this solves the problem</b>: The new material has same desired electrical properties but is physically thicker, and hence reduces leakage by 10,000X.

<b>Problem 2</b>: Unwanted current flow from source to drain when transistor is "off"
<b>Why this is a problem</b>: As transistors get smaller, current flows between the source and drain even when it should not. This leads to transistors that can appear to be incorrectly "on" and will cause many problems.

<b>New solution</b>: Insert a layer of insulator (oxide) under the transistor
<b>How this solves the problem</b>: The oxide layer blocks the path of this unwanted current flow, reducing it by 100X.

<b>Problem 3</b>: High voltage needed, thereby increasing power usage
<b>Why this is a problem</b>: The addition of the oxide layer to fix problem 2 increases resistance in the source and drain. Higher resistance must be overcome by higher voltages and causes greater heat.

<b>New solution</b>: Make the source and drain thicker
<b>How this solves the problem</b>: Thicker source and drain reduce resistance by 30%, giving the electrons more mobility. Less voltage is required with less resistance and heat is reduced considerably.


In addition to solving these 3 problems, the TeraHertz transistor has 3 other beneficial features:

<b>Feature 1</b>: Low junction capacitance
<b>Why needed</b>: Electrical effect at the periphery of the source or drain which slows down electrons

<b>TeraHertz transistor solution</b>: Source and drain abut buried oxide layer
<b>Benefit</b>: Allows transistor to run faster

<b>Feature 2</b>: Alpha particle immunity
<b>Why needed</b>: Stray radioactive particles arrive from atmosphere or package which can lodge under transistor and affect its behavior

<b>TeraHertz transistor solution</b>: Region above buried oxide layer is very thin, leaving almost no space for alpha particles
<b>Benefit</b>: Increased reliability

<b>Feature 3</b>: No "floating body" effect
<b>Why needed</b>: Charge can get trapped between the gate dielectric and the buried oxide layer, affecting behavior of the transistor

<b>TeraHertz transistor solution</b>: Region above buried oxide layer is very thin and cannot collect charge during transistor operation
<b>Benefit</b>: Ease of circuit design


Intel is very excited about having developed the TeraHertz transistor. By addressing the power problem, it paves the way for the continuation of Moore’s Law through the end of the decade. This will enable end user applications that are beyond our imagination today.

As with any new technology, there are numerous technical issues that need to be
resolved before volume production can begin. Intel believes that the TeraHertz transistor architecture will become the clear choice for the second half of the decade.

For more details about Intel’s TeraHertz Transistor architecture and other Intel
research developments, please visit <A HREF="http://www.intel.com/research/silicon" target="_new">http://www.intel.com/research/silicon&lt;/A>.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 26, 2001 11:03:14 PM

WOW!!! I hope it works the way they say it will. Good Job Intel.

Also, I wonder how soon will they be able to use this technology. Can they use it with any mfgr technology like 0.13u or 0.09u. How much extra will it cost to make the special wafer.

Well I am excited about this. Just guess the applications of the really fast processors. Finally, I will be able to play a REAL "Virtual Reality game."

KG.
November 26, 2001 11:20:55 PM

hey! good job there Ray!
i noticed you have been absent for a week or so now... and please, dont be modest, we all know u invented this in your spare time, not intel *GRINS*

Excuse me for a moment. I need to drive my ergonomic wheely chair over a sheet of bubble wrap!
Related resources
November 26, 2001 11:21:35 PM

hey! good job there Ray!
i noticed you have been absent for a week or so now... and please, dont be modest, we all know u invented this in your spare time, not intel *GRINS*

course the next question is:
how the hell do we find a memory interface that can remotely match that lol

Excuse me for a moment. I need to drive my ergonomic wheely chair over a sheet of bubble wrap!
November 26, 2001 11:23:15 PM

I’m definitely not the most connected person, but this thing never leaked. This is the first I’ve heard of it. With that transistor density, the idea of a full-fledged computer on a chip becomes darn near viable.

Possibly VIAable if licensing issues can be worked out.
November 27, 2001 2:39:49 AM

I'm confused.
Is the main advantage that they go faster or produce less heat..

I'm thinking that the whole idea is that they can go faster while producing the same heat per unit area of the die. is this right???

What's the improvement over current tech??
we know Intel can get their whole CPu to run at 2GHz, which means the transistors are at least in excess of that... but is 1,000 Ghz 100 times better than current tech.

or is it only 5% better.. eg. current trannies run at 950 GHz.

just asking... making you stress your brain..

OT:
You seem to be held up as a guru of sorts.. like the ULTIMATE CPU knowledge base..
Do you work for Intel??
What's your background??
Nice to see some real info.

balzi

"I spilled coffee all over my wife's nighty... ...serves me right for wearing it?!?"
November 27, 2001 3:11:18 AM

Quote:
The source and drain are variants of the basic silicon and the gate is a material called polysilicon. Below the gate is a thin layer called the gate dielectric. It is made of silicon dioxide today. All CMOS circuits today are made of transistors such as this, hooked up to each other by interconnects (wires). The Pentium 4 processor has 42 million such transistors on a fingernail-sized piece of silicon.


Not variants, but doped areas of the silicon, its still the same silicon substrate, but with impurities added to change its electrical properties.

Size of a thumbnail? Maybe andrea the giants thumbnail, but the p4 core is pretty damn big heh.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 3:13:58 AM

Quote:
New solution: Replace silicon dioxide with a new material with a "high k" value
How this solves the problem: The new material has same desired electrical properties but is physically thicker, and hence reduces leakage by 10,000X


hate to break it to you rayy, but intel arent the only ones who have been working on/using high k dielectrics, a quick jaunt to www.siliconstratagies.com will show you that. Giving intel credit for "inventing" this breakthrough is rather unfair.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 3:16:34 AM

Quote:
How this solves the problem: The new material has same desired electrical properties but is physically thicker, and hence reduces leakage by 10,000X.


Wrong, the material is PHYSICALLY as thin but has a higher dielectric resistence.(hence the high k dielectric part). The thickness of the gate oxide controls how fast the gate can switch on and off, thinning this gate leads to faster on off times, but it also leads to leakage as you mentioned. The high k's keep the same(or even more so) level of thinness but maintains the resistance to electricity required to prevent leakage.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 3:19:14 AM

Quote:
Problem 2: Unwanted current flow from source to drain when transistor is "off"
Why this is a problem: As transistors get smaller, current flows between the source and drain even when it should not. This leads to transistors that can appear to be incorrectly "on" and will cause many problems.

New solution: Insert a layer of insulator (oxide) under the transistor
How this solves the problem: The oxide layer blocks the path of this unwanted current flow, reducing it by 100X.


This is SOI technology, and we know who is pioneering that, however it would not help source/drain leakage, it lowers capacitance which makes the transistors switch faster(and cooler due to less electrical resistance.)


This is NOT an insult so please dont take it as such. But,
Did you write this? or are you cutting and pasting from somewhere, because this "technical" information has alot of misconceptions and flaws.



"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 3:22:24 AM

He works for intel, no he cant tell you anything secret due to his NDA.


I work for fujitsu/AMD, I will tell you whatever you want to know if you buy me dinner first.

Nice to meet you.



^joke

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 5:18:18 PM

"Is the main advantage that they go faster or produce less heat.."

Both up to a certain point. If you push them fast enough eventually the heat will surpass that produced by the slower older transistors. But these speeds would be well in excess of what the old technology is capable of reaching.


"or is it only 5% better.. eg. current trannies run at 950 GHz"

Current transistors are much larger and cap at approximately 100GHz. The TeraHertz transistor can switch data about 10 times faster than this.


"What's your background??"

I work for Intel. You can click on my name to get some more information.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 27, 2001 5:22:58 PM

"Not variants, but doped areas of the silicon, its still the same silicon substrate, but with impurities added to change its electrical properties."

I would call that a variant. This is just a question of definitions.


"Size of a thumbnail? Maybe andrea the giants thumbnail, but the p4 core is pretty damn big heh."

Actually, it is fairly small. Have you ever seen one that was not covered by the heat spreader?

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 27, 2001 5:25:05 PM

Raystonn -- To set the record straight, what you described is basically fully depleted SOI with high k gate dielectric, which has been trumpeted and published in public forums (such as IEDM) by other companies and entities (such as universities) for years. In fact, IBM has products out with SOI, although it favors partially depleted SOI for now because it is much easier to implement.

The fact is Intel provided little or no contribution in the advancement of high k or SOI. If you don’t believe me, you can go and do a literature search on those subjects using INSPEC or Web of Science. In fact, they have been going out their way to knock the SOI effort of IBM. It is not unlike the case of copper interconnect; they told everybody IBM was wrong and it’s not really needed while quietly ramping up the effort. In a typical Intel move, they now behave as if they had invented everything related to fully depleted SOI with high k.

There is no question if Intel can deliver what specified in the press release, it will be a great engineering accomplishment. However, that does not change the fact of its questionable practice of intellectual integrity.


**Spin all you want, but we the paying consumers will have the final word**
November 27, 2001 5:27:05 PM

"hate to break it to you rayy, but intel arent the only ones who have been working on/using high k dielectrics, a quick jaunt to www.siliconstratagies.com will show you that. Giving intel credit for "inventing" this breakthrough is rather unfair."

Did I ever say Intel invented high k dielectrics? No. Intel is however the first and only one to incorporate it into the design of a new transistor. Please do not turn this into a thread about companies. I would rather discuss the technology itself.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 27, 2001 5:35:59 PM

"Wrong, the material is PHYSICALLY as thin but has a higher dielectric resistence"

No. It is also thicker. Go read the technology briefs to which I pointed you. It will help your arguments to know something about the subject matter at hand. The new material will be a thicker physical film while retaining the same capacitance.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 27, 2001 5:44:35 PM

"This is SOI technology"

It is an adaptation of SOI technology. The new transistor uses Depleted Substrate SOI. It is called a DST (Depleted Substrate Transistor.) This is in comparison to partially depleted SOI, which is used by others.


"it would not help source/drain leakage, it lowers capacitance which makes the transistors switch faster(and cooler due to less electrical resistance.)"

The depleted substrate eliminates leakage paths through substrate. This is all clearly outlined in <A HREF="http://www.intel.com/research/silicon/micron.htm" target="_new">these</A> resources. Please read through them.


"this 'technical' information has alot of misconceptions and flaws."

So far the only real flaw is that you did not read it.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 27, 2001 6:39:13 PM

Ok, I made 2 small mistaked in my replies to your thread rayy.

One, was that I replied to your thread BEFORE reading your links.(assumed you copied and pasted the pertanent data.
Two, was that I misrepresented my line about the thickness of the gate oxide. I did not mean to say that you were wrong saying it was thicker.


Here is what I meant to say.

The majority of speed increases of transistor switching has come from thinning the gate oxide to speed up the transistors ability to switch off and on, this however comes with a price, namely electron leakage from the gate to the channel. The high k dielectrics resist electricity better, so that you CAN have a thinner layer of gate oxide without as much leakage.

That having been said, from the links you posted and other things I have read. Intels new gate oxide material HAS to be thicker(my guess would be its a new material and needs to be thinned down with process advances) this will have a negative effect on transistor switching speed.(most likely overcome by the other speed enhancing features of the new transistor design.)

BTW, there is very little leakage from sourse to substrate, soi is purely for reducing capacitance in the transistor, not for reducing leakage.(UNLESS INTELS NEW PROCESS CAUSES LEAKAGE TO THE SUBSTRATE WHICH i AM UNSURE OF!!!!!)

The press release is kind of vague. When is a in depth tech release coming?



as for the claims of inventing the whole technology, this post sums up my comments.
http://www.realworldtech.com/forums/index.cfm?action=de...


"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 6:43:06 PM

"It is an adaptation of SOI technology. The new transistor uses Depleted Substrate SOI. It is called a DST (Depleted Substrate Transistor.) This is in comparison to partially depleted SOI, which is used by others."

Once again, fully depleted SOI has been around for years, about as long as partially depleted SOI, and many entities (companies and universities) have published work about it. The reason companies like IBM (or AMD) are using partially depleted SOI first is that it is easier to implement. Please do not compare something already in product (partially depleted) to something only on paper (fully depleted)


**Spin all you want, but we the paying consumers will have the final word**
November 27, 2001 6:43:18 PM

I agree with bhc, that was the point of most of my posts. The technology is nice, but intel did not invent it.


Rayy, about intel being the first to make a high k transistor, this is not true, ibm and many other fabs have done plenty of research wafers which use high k dielectric, perhaps intel is close to releasing theirs to market, but from the links you provided it seems to still be in the experemental stage, which puts them right with ibm, amd, and everyone else.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 7:01:39 PM

"The press release is kind of vague. When is a in depth tech release coming?"

I have posted links to the technical information a couple times now. <A HREF="http://www.intel.com/research/silicon/micron.htm" target="_new">Here</A> it is again. Have a look.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 27, 2001 7:17:15 PM

"The technology is nice, but intel did not invent it"

Intel did invent the first high k dialetric, fully depleted SOI transistor that is capable of switching over one trillion times per second. Thus it is named the TeraHertz transistor. Our researchers have created them, so this is not a paper announcement. These transistors now exist, in small quantities.

Did Intel create high k dialectrics? Probably not. Did Intel create wires and discover electricity? No. Do either of those matter? Not really. Everyone stands on the backs of everyone else. What matters is the resulting end technology.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 27, 2001 10:21:48 PM

Intel may have been the one to make a press release putting all these things together, but that does not mean they invented it, like I said, many companies have working enginnering samples of high k and soi, and as others have stated, intel has been against soi and other advances for a while, untill they catch up and try to claim credit.

But this is I agree off topic.

An interesting side effect of the new material for the gate oxide is it having higher thickness than the current SIO. This increased thickness will slow down the gates switching speed due to the additional distance from the gates charge and the channel. I wonder how intel has combated this(or if they plan to thin the gox in future revisions.)

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 27, 2001 10:55:38 PM

Raystonn -- TeraHertz-Transistor is just a marketing buzz word created by your company (Intel). Picosecond or sub-picosecond gate delays have already been published before (see e.g. 2000 IEDM Tech. Digest, P. 45, or Proc. of 2001 Sym. of VLSI Tech., P. 9). It's just that nobody bothered to call them "TeraHertz-Transistors" before.

Moreover, it's one thing to make "fast" transistors, which good for PR, it's another thing to make transistors with high drive current, which is much important in circuit speed. So far, everyone had a hard time to keep the drive current high while reducing the supply voltage. Intel was no exception. I assume your company will make a technical presentation in the 2001 IEDM next month. I would reserve my full judgment until then.

Nevertheless, fully depleted mode, high k gate dielectrics and raised source/drain are not only all been well published but also parts of evolutionary path of the SOI technology. I am NOT dissing Intel's effort here (not like Intel, which has the propensity of dissing others' work until it decides to join in). In fact, I would credit Intel researchers for putting all three things together and successfully making working transistors. However, the fact remains "TeraHertz" is basically a marketing hype, not a really scientific/engineering breakthrough.

**Spin all you want, but we the paying consumers will have the final word**
November 27, 2001 11:02:59 PM

"but that does not mean they invented it"

Yes, it does. When you are the first to put together object A and object B to create an object C it is said that you have invented object C and can in fact patent it if this is desired. This is the way it has always been done. Noone ever creates anything from scratch. This is impossible due to the law of conservation of mass and energy. Everything that will ever exist already exists today. The only ingenuity present in invention is putting them together in new and exciting ways.


"This increased thickness will slow down the gates switching speed..."

No, the purpose of the new substance is to maintain the same electrical properties while increasing the thickness. The increased thickness reduces leakage, but the resistance is not increased. This is because of the properties of the high k dielectric. If the same silicon dioxide had been used and the amount had been increased to make it thicker, then yes, it would have slowed everything down. But that is not the case here.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 28, 2001 12:09:13 AM

Raystonn -- Two questions.
1. Intel published some results on "traditional" (i.e. bulk substrate, not SOI) 25/30nm gate-length transistors late last year and early this year. As far as I know they were the first devices made by Intel that achieve 1 picosecond ring-oscillator gate delay. Why are they not called TeraHertz transistors??

2. Those devices were done with "traditional" silicon dioxide of ONLY 0.8 nm thick (about three atomic layers). At that time, the stance of your company was, "We don't need SOI and high k - see what we can make." Of course, nobody in the silicon IC technology community really believed them. Judging from your articles, they themselves don't either. So, why keep saying that in science conferences/forums??

**Spin all you want, but we the paying consumers will have the final word**
November 28, 2001 12:56:01 AM

"Why are they not called TeraHertz transistors"

If they were capable of switching over one trillion times per second then they could have been given this name. If this is so then the question would have to be punted to whatever department does the labelling.


"why keep saying that in science conferences/forums?"

Why keep saying what? Could you point me to an article or two where Intel states they will never need or use SOI? I certainly have not said that myself.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 28, 2001 2:39:18 AM

"... the question would have to be punted to whatever department does the labeling."

That is exactly my point -- this labeling is pretty much a marketing decision, not a scientific one. BTW, sub-1 ps (picosecond) RO gate delay basically translates into, in layman's term, "switching over one trillion times per second."


"... an article or two... never need or use SOI?"

Of course, Intel would never say never, but it just kept making misleading claims over the years.

A quick search on EE Times for SOI:

<A HREF="http://www.eetimes.com/story/OEG20011126S0031" target="_new">http://www.eetimes.com/story/OEG20011126S0031&lt;/A>
This is the latest EE Times article: "After having downplayed the benefits of silicon-on-insulator transistor technology for years, Intel Corp. now will spin its own version, ..."

<A HREF="http://www.eetimes.com/story/OEG19991209S0002" target="_new">http://www.eetimes.com/story/OEG19991209S0002&lt;/A>
Note the fully-depleted SOI paper published by UCB two years ago. Does "thin body" sounds familar

<A HREF="http://www.eetimes.com/story/OEG20001215S0009" target="_new">http://www.eetimes.com/story/OEG20001215S0009&lt;/A>
"Bohr and his colleagues detailed Intel's objections to SOI at the VLSI technology symposium last June. He remains unmoved today, insisting that Intel researchers see no benefits to SOI over the long term."

**Spin all you want, but we the paying consumers will have the final word**
November 28, 2001 4:04:22 AM

BTW, the last article was dated last December (2000 IEDM). There can be no question the project Intel publicizes today was at least being actively pursued at that time, if not already half-done, since the deadline of 2001 IEDM paper submission is the end of June.

**Spin all you want, but we the paying consumers will have the final word**
November 28, 2001 4:20:01 AM

I'm on Raystonn's side here.
If Intel did indeed manufacture or at least build the first pico-second switching transistor then why can't they claim teh credit???
i also agree with him here -> this is all boring Intel v. AMD trash... who cares??

Stuff I want to discuss is
- Who has SOI (or variants of SOI like teraHertz gates) earliest in their real road-map...
- Who will produce chips using SOI first??
- Which current processor Architecture will make best use of faster transistors.. in terms of pipe-line speed increases vs. stage length, change-over time.. balance of ALU/FPU etc modules allowing for nice syncing of ativities..

ie. AMD has a different cache setup... will faster internal clock speeds actually make it's memory defficiencies more noticeable, or NOT???

lastly, I would like to point out. Matisaro and Raystonn, we (at least bhc and myself) would probably appreciate and will certainly respect your opinions more if you remain as objective as possible. not saying you haven't been, just pointing it out... please don't respond to this comment and argue about who's the most objective ra ra ra...

here's to soem good ol' fashioned thoughtful discussions. (actually i'm probably to young to know about "ol' fashioned")

balzi

"I spilled coffee all over my wife's nighty... ...serves me right for wearing it?!?"
November 28, 2001 4:37:49 AM

Ok,
my first comments and food for thought on this (new) subject.

I would suggest that Intel may have got a good thing on their hands, but AMD and others won't be far behind... I've seen SOI toted as the newest tech. to storm the AMD road-map. it's target release is some-time coming... I think it's the hammer line, but maybe even the barton and appaloosa will use it (memory gone rusty)
So if this is true then Intel's "discovery/creation" won't put them to far in front.

But if the Northwood comes out with lots of cache (say 1MB all up) then it'll have more chance of making good use of a instruction pipe-line that executes REAL fast...
of cource the Barton core might do similar.. (side-note, the next Athlon core is called Barton isn't it?? )

also, matisaro and Raystonn can help here, how are the current cores shaped to handle a faster gate speed. Are they well balanced?? I know you'll say "yes balzi, they are well balanced"... can we get some indication.. what have you done to allow for this.... ie. precise stage design.. or something.

also, if this tech. loosens the leash that holds clock-speeds back.. then won't memory speeds (FSB -> memory link, not cache or HD) just hold everything back, kinda like saturating your FSB and having your processor sit and wait...
who cares if it can wait 90 billions times more pre second than it used to be able to.

anyone, out with conflicting, agreeing, lemon-flavoured or battery-powered idea's out there???

|:) 

"I spilled coffee all over my wife's nighty... ...serves me right for wearing it?!?"
November 28, 2001 8:49:14 AM

Funny you should say the 'P4's die is about the same size as a fingernail' Raystonn because I very recently came across this link:<A HREF="http://www.overclockers.com/articles486/" target="_new">http://www.overclockers.com/articles486/&lt;/A> showing a P4 with the heat spreader ripped off.

I dont want to get into petty arguements but I think the picture clearly shows the P4 die is 'roughly' the same size as the person's <b>thumbnail</b>.

Do you agree ?

P.S Could you give use any info about the rollout of 533 FSB and 845E chipset?? Rumours are they will out 2Q02 (Source:<A HREF="http://www.ebns.com/story/OEG20011126S0077" target="_new">http://www.ebns.com/story/OEG20011126S0077&lt;/A>) most likely coinciding with the Northwood launch. It would also be interesting if Intel produce a DDR based 533 FSB Northwood chipset...

<A HREF="http://www.jc-news.com/index.cgi" target="_new">Source</A>
<font color=blue>The Pentium 4's connection to its chipset will, in next year's second quarter, be upped from the familiar 400/100MHz to a more aggressive 533/133MHz, which will (in conjunction with Northwood's cache bigness) increase Intel's competitiveness in the x86 marketplace. If both main x86 makers keep their current schedule, Intel looks to be the more likely claimant for the performance crown (as of, say, next June).
There is one modifier to this, though: For a 533/133MHz chipset to truly make for an effective boost over current top line 400/100MHz chipsets (that'd likely be, as some suggest, SiS's DDR333 compatible 645 chipset), the chipset would have to support a memory subsystem faster than what is currently available. That means, in my mind, that Intel will have to mandate one of the following three possible options: (A) DDR SDRAM running at higher than 333/166MHz speeds; (B) dual channel DDR SDRAM; or (C) dual channel PC1066 DRDRAM. I personally do not believe that holding the already available single channel DDR333 memory subsystem and only increasing the cpu side of the chipset would result in much of a palpable performance difference. Luckily, of the above three options, we know that the third is doable, we've seen the second for other platforms and we've seen it demoed, I believe, for the P4, and the first option has potential, but only if Intel increases pressure on DDR SDRAM research.</font color=blue>

<font color=purple>~* K6-2 @ 333MHz *~
I don't need a 'Gigahertz' chip to surf the web just yet ;-)</font color=purple>
November 28, 2001 1:27:29 PM

Quote:
No, the purpose of the new substance is to maintain the same electrical properties while increasing the thickness.


Yes raystonn it will.


The gate oxides properties do NOT affect gate switching speed, all the gate oxide is there for is to prevent leakage from the gate to the channel. The THICKER the gate oxide the slower the transistor takes to switch on and off because of the distance between the electrostatic charge of the gate and the doped silicon in the channel. Thinning the gate oxide brings the esc closer to the channel allowing it to affect it much faster, resulting in.
A: faster cycle time
b: more leakage.

The NEW material that intel has devised has a HIGHER electrical resistance, meaning it can resist electricity at the same level as sio while being able to be MUCH THINNER. Why the first generation of this material is thicker is beyond me, as this would UNDOUBTEDLY lead to slower operation.(which is probably overcome by the other advances lest you release a slower transistor).

When they perfect their methods for this new gate oxide material, and are able to make it thinner, the transistor will perform even faster.

Quote:
The increased thickness reduces leakage, but the resistance is not increased. This is because of the properties of the high k dielectric. If the same silicon dioxide had been used and the amount had been increased to make it thicker, then yes, it would have slowed everything down. But that is not the case here.


Yes the resistance DOES increase, thats what "high k" means, high resistance. The current gate material has a set amount of electrical reistsance, at a certain thickness it can no longer resist the electicity in the gate, this causes leakage, making it thicker is one solution, but a thicker gox leads to slower transistor function, INTEL has invented a new gate material which has a HIGHER RESISTANCE, this would allow them to use a thinner layer and not have leakage. Thus the transistor will run faster.


"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
Anonymous
a b à CPUs
November 28, 2001 2:39:12 PM

I cant shake off the idea Raystonn is nothing but a nickname for intel's PR department. Polite posts, technically savvy, mostly interesting, but always biased.

Thats all fine with me, as it still results in interesting discussions that generally rise above the level of AMDmeltdown's posts.. but I cant believe how much free time intel software engineers have, to post on boards such as here... Shouldnt you be working on SSE2 and IA64 compilers anyway ?

= The views stated herein are my personal views, and not necessarily the views of my wife. =
November 28, 2001 7:28:54 PM

Sometimes when rayy posts things I dont believe of disagree with, I have been loathe to call him on it, as his knowledge of software is undoubtedly higher than mine. This time however, he is treading in my territory, I work at a fab and gate lengths and gox thickness is what I deal with everyday.(well actually its defect anaylisis, but the fundamentals are shared.). So I am up for a nice debate/discussion of this new technology.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!
November 28, 2001 8:32:11 PM

"Do you agree?"

Yes. Some fingernails are larger than others.


"Could you give use any info about the rollout of 533 FSB and 845E chipset?"

Northwood with a 400MHz FSB will begin shipping in mass quantities mid next month. They will be available for sale officially in the beginning of January. A Northwood designed for use on a 533MHz FSB will probably be out in about a half year from now, but overclockers can always increase their FSB anyway. Dual channel PC1066 RDRAM motherboards will probably be out when the 533MHz FSB Northwoods are officially released. DDR266 i845 will be out next quarter some time.


"It would also be interesting if Intel produce a DDR based 533 FSB Northwood chipset..."

This would require DDR533 or a dual-channel DDR266 chipset. Dual-channel DDR is planned eventually with the Plumas chipset for the Xeon. I do not foresee it happening for the Northwood Pentium 4.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 28, 2001 8:54:55 PM

"I'm on Raystonn's side here.
If Intel did indeed manufacture or at least build the first pico-second switching transistor then why can't they claim teh credit???"

I see you are a newbie. Welcome. Of course, Intel can call whatever devices by whatever name they want to call. I merely want to show “TeraHertz” is more of a marketing buzz word than a true mark of the first arrival of transistors capable of picosecond switching since they have been done before. By the way, the two examples I cited in one of my previous posts are actually from Intel (a non-SOI structure) and AMD. Both of them were published well before this latest Intel press release on “TeraHertz” (fully depleted SOI structure).

As for my complains about Intel’s public stance regarding SOI, copper, etc has been quite underhanded, I can actually understand their motive – marketing again; until they catch up, they don’t want to allow any public perception that a competitor (e.g. IBM) is leading them down a certain technology path. However, it’s sad that in a company of great engineers (Moore, Grove, etc.), marketing is really the king now.

As for details of this technology, I hope to learn more next week at 2001 IEDM. I won’t comment further other than what I already did.


**Spin all you want, but we the paying consumers will have the final word**
November 28, 2001 9:03:24 PM

"I cant shake off the idea Raystonn is nothing but a nickname for intel's PR department. Polite posts, technically savvy, mostly interesting, but always biased. "

I wonder about it sometimes too. However, so far I'm willing to give him the benefit of the doubt.

**Spin all you want, but we the paying consumers will have the final word**
November 28, 2001 9:10:08 PM

Northwood + a p4 derived Nforce running dual PC2100 - PC2700 DDR would be nice.

Excuse me for a moment. I need to drive my ergonomic wheely chair over a sheet of bubble wrap!
November 28, 2001 9:12:25 PM

Unfortunately, the nForce only delivers half of its memory bandwidth to the processor. A Pentium 4 would be starved for data on a similarly designed nForce chipset.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
November 29, 2001 3:58:45 AM

let's ditch the who created SOI/terahertz/copper/oxygen .. it doesn't matter.
I am willing to let Intel and AMD worry about who did whatever first.

I matters nothing, teh real stuff.. is who's gonna implement it..
in what process.. when. . . How.. what kind of SOI??? .. .

and then let's talk about some alternatives...
everyone's gone off on the brilliant blue yonder of "intel did na create nuffin'".. "..but AMD did na git it werkin' firs'"

DROP IT PLEASE.
or should i start a new thread.

Balzi

PS. what does newbie men anyway.. expect that I haven't posted 1000s of times of something (what is the limit anyway?? I've held this brand for a while)

"I spilled coffee all over my wife's nighty... ...serves me right for wearing it?!?"
Anonymous
a b à CPUs
November 29, 2001 4:43:15 AM

I have a couple of minor complaints about your info, feel free to right any wrongs I create here.

Gate oxide leakage is actually a tunneling current, which results in values that V=IR will never get you. The oxide thickness does affect the gate oxide leakage current, only following a different curve than V=IR. The K referred to in previous threads is more than a description of a substances resistivity, it is also a qualifier for a dialectric.

"Yes raystonn it will."

I disagree, or at least throw in an emphatic *not* necessarily*. By using a high K gate oxide material one is able to make the following rearrangement: thicker gate oxide. Why? This does get you less leakage current (according to some tunneling curve), but it allows this to occur while keeping Miller capacitance levels up. Since it is actually the value of this capacitance with respect to gate current which is responsible for switching speed, then if the capacitance is the same, then the speed is unaffected.

"Why the first generation of this material is thicker is beyond me"

I think more than anything this has all been done to reduce overall power consumption. A couple pico amps multiplied by 41 zillion (or whatever) adds up. I would say it heats things up as well, but I'm less informed about the physics of tunneling (I'm not even sure I believe in it). I.e. does it cause heat like a current through a resistance?
November 29, 2001 4:50:10 AM

i read an article a few months back about apple's G5, that will feature SOI <A HREF="http://www.theregister.co.uk/content/39/22328.html" target="_new">here</A>. another good one about some of the features on the upcoming g5 and the chipset <A HREF="http://www.theregister.co.uk/content/archive/21692.html" target="_new">here</A>. and it also looks like apple might make a buyout bid for the powerPC tech, <A HREF="http://www.theregister.co.uk/content/archive/20038.html" target="_new">here</A>.
again in regards to balzi's statement, please no mac vs pc stuff or anything like that. i'm just starting to getting interested in this side of hardware and starting to pick up a little bit of this all. this thread has been really interesting thus far :D 
November 30, 2001 12:32:31 AM

mbetea - If you are interested in reading about IC fabrication technology advances, EE Times in general has done a pretty good job. For someone right in the forefront of the technology R&D, their articles on IEDM (International Electron Devices Meeting, early December every year) and VLSI Technology Symposium (mid June every year) are sometimes a little too simplistic. Still, they are usually quite informative regarding future technology directions. You can get it online www.eetimes.com.

balzi - This is not about Intel-vs-AMD. Don't skew the issue here. In fact, IBM is the one company has SOI products in the market. Neither Intel nor AMD can claim that. AMD is trying to get the IBM SOI technology, while Intel just starts to publish some transistor and small circuit results. Let's get the record straight here.


**Spin all you want, but we the paying consumers will have the final word**
November 30, 2001 1:31:41 AM

Yellowstone will be release in this time.wich can get near 100 GB/S.

Anyway there a whole lot of new tech that will be release in this time.

Wisdom dont come with time
Meilleur chance la prochaine fois
November 30, 2001 2:26:34 AM

bhc,
sorry, I must have been to vague.. you see,, we are in agreement. I DO NOT WANT ANY INTEL VS. AMD ranting.
I want to see some discussion of what improvements on current technology from AMD and Intel and VIA and anyone.. SOI can give..

see all my previous posts. I don't care about the AMD vs. intel debate.. just let's talk about SOI and it's little variants.

you however seem determined for me to be in the wrong.

I'm just wanting to hear other people's opinions.. I figured asking for opininos would be a welcome change from "Shut up", "you suck".. "AMD rocks (but I have no real opinion)"

that sort of trash...

my one side issue is for Raystonn and Matisaro to be as objective as their bosses will allow them.. heehe


"I spilled coffee all over my wife's nighty... ...serves me right for wearing it?!?"
November 30, 2001 12:05:52 PM

Boring........................................
ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ.
November 30, 2001 5:00:30 PM

Please don't do that :( 

If you need to take a crap, go to the restroom. Don't do it in this thread.

<font color=orange>Quarter</font color=orange> <font color=blue>Pounder</font color=blue> <font color=orange>Inside</font color=orange>
November 30, 2001 10:16:53 PM

thanks for the link bhc! weekend is here, i'll be doing some reading :smile:
Anonymous
a b à CPUs
December 2, 2001 10:30:01 PM

I've been meaning to post in this thread for a while, but haven't had time. I was going to point out that this is just SOI, something Intel spent a lot of effort bad mouthing, but others beat me to the punch. Then I was going to point out Matisaro's misunderstanding on what high-K dielectric means, but knewton just beat me.

The K in high-K stands for the dieletric constant of the gate insulator. It has nothing to do with resistivity, instead it has to do with the capacitance of the gate. The normal silicon dioxide has a K of about 4. As transistor size and voltage drops, it is harder for the gate to control the electrons in the transistor. The capacitance of the gate becomes too small to attract/repel enough electrons.

To increase the gate capacitance, you can make the gate thinner or increase K. The problem with making the gate thinner is the tunneling current. Gates are getting so thin that they literally count the atoms to measure the thickness. The most advanced processes (like 0.13 and 0.10 micron) have gates 12 to 20 atoms thick. Not only is tunneling current a problem, but making gates without pinholes (shorting gate to transistor body) is a problem.

Tunneling current exponential rather than linear. 20 atoms and above will have basically no tunneling current (I think down to 15 is still good, but my memory is hazy). Getting to 10 atoms and below will give currents that can be hundreds of times larger. Imagine a P5 that uses 500 watts at zero Hz (due to tunneling current) and 550 watts at 5 GHz.

If you use a material with a K of 20 then a 10 atom SiO2 layer becomes a 50 atom high-K layer. They use a thicker layer, rather than thinner, because that was their goal. It allows them to continue making the gate thinner for several more years, until they have to find an even higher-K material.
!