no idea about the cache, but will debut at 1.6 GHz and 166 MHz (333 DDR) FSB in later revisions thanks to the new 0.13 micron process, that will save a lot of die space which could be used for the extra L2 cache of 512k. But I guess they will make a server/MP version with 512k and a desktop version with 256k and SMP disabled, just like PIII Tualatin.
<font color=red>No system is fool-proof. Fools are Ingenious!</font color=red>