Ok....I've been pondering this in my head for a long time now, and I just don't know what to think of it....the only thing I can come up with is that it is VERY impressive to say the least...now read on to find out what I'm talking about...
All Socket A processors use a cache data-path (for L2 cache anyways) that is only 64-Bit's Wide....now, that is a VERY narrow bandwidth is it not ?? Especially compared to all Pentium III Coppermines and better (Tully, P4W & NW) which is 256 Bit's Wide.....
Now....The Athlon's (all of them) only have this 64 bit wide cache interface and it STILL outpaces the P3.....Tully, and P4 Willy in the majority of cases.....
Now, could this 64-bit data-path be castrating the Athlon ??
Example.......The unexplained reason why the P4 outperforms the Athlon in Time Demo's of Q3A....its by a significant margin aswell....could this be due to the data-pathway of the L2 cache architecture ??!?? Like, what would happen if AMD but a 256bit wide data-pathway on the Athlon now for thwe L2 Cache?? Would it than have a negligable performance increase? or would it be significant?
This 64-bit L2 cache data-pathway interface is the only thing I can really think of right now that would explian this unexplained experience in Q3A.....we know its not totaly due to the P4 running the Quad pumped FSB, as it still remains when running either DDR or RDRAM on the P4 Platform.....so the cache architecture is what comes to my mind, and I did a bit of research on it, and the Athlon is STILL running with this 64-bit data-pathway and it can totaly compete with the Intel Counterparts......is this good engineering on part of the K7 Architecture or just coincidence?? I'd really like to know.....anyones thoughts, comnments? All is appreciated...
-MeTaL RoCkEr
My <font color=red>Z28</font color=red> can take your <font color=blue>P4</font color=blue> off the line!<P ID="edit"><FONT SIZE=-1><EM>Edited by MeTaLrOcKeR on 01/11/02 11:39 AM.</EM></FONT></P>
All Socket A processors use a cache data-path (for L2 cache anyways) that is only 64-Bit's Wide....now, that is a VERY narrow bandwidth is it not ?? Especially compared to all Pentium III Coppermines and better (Tully, P4W & NW) which is 256 Bit's Wide.....
Now....The Athlon's (all of them) only have this 64 bit wide cache interface and it STILL outpaces the P3.....Tully, and P4 Willy in the majority of cases.....
Now, could this 64-bit data-path be castrating the Athlon ??
Example.......The unexplained reason why the P4 outperforms the Athlon in Time Demo's of Q3A....its by a significant margin aswell....could this be due to the data-pathway of the L2 cache architecture ??!?? Like, what would happen if AMD but a 256bit wide data-pathway on the Athlon now for thwe L2 Cache?? Would it than have a negligable performance increase? or would it be significant?
This 64-bit L2 cache data-pathway interface is the only thing I can really think of right now that would explian this unexplained experience in Q3A.....we know its not totaly due to the P4 running the Quad pumped FSB, as it still remains when running either DDR or RDRAM on the P4 Platform.....so the cache architecture is what comes to my mind, and I did a bit of research on it, and the Athlon is STILL running with this 64-bit data-pathway and it can totaly compete with the Intel Counterparts......is this good engineering on part of the K7 Architecture or just coincidence?? I'd really like to know.....anyones thoughts, comnments? All is appreciated...
-MeTaL RoCkEr
My <font color=red>Z28</font color=red> can take your <font color=blue>P4</font color=blue> off the line!<P ID="edit"><FONT SIZE=-1><EM>Edited by MeTaLrOcKeR on 01/11/02 11:39 AM.</EM></FONT></P>