How many engineers does it take to change a few bridges? The move to a 166MHz FSB shouldn't require <i>any</i> new engineers to implement.
They're already doing a die shrink, which requires planning, implementation time, and testing. Then they're doing a switch over to SOI which requires at the very least testing. They're already going to be changing the bridges anyway just for the new clock speeds. So at the very most if AMD moved to a 166MHz FSB, it would still require no more man-hours than what they are already doing.
True, the cache would be nicer to see, but even still, anything is better than nothing, which is what AMD has planned.
Speaking of cache, it would take a whole 1 additional engineer at most to implement.
Millions? I'm not talking about any major change. Just up the cache a little and set it to a FSB default of 166MHz, which most overclockers can already do anyway, and which VIA already officially supports a chipset for.
<pre>If you let others think for you, you're the
only one to blame when things go wrong.</pre><p>