Crashman P3 1.266, 1.4

[Unolocogringo]

I've been looking at one of these to play with. My question is. Will they work in a desktop board? According to Intels websit it says that the, 1266s and 1400s with512k are the only versions available. If you look up the S-Spec on these chips it says they are for server motherboards. Not supported in a desktop motherboard. The slower 1200 with 256k says for desktop motherboards, not reccomended for server boards.

So did intel decide to stop at 1200 for desktop Tualatins?

I aint signing nothing!!!

 

[jclw]

Any i815 B-step or VIA 133T/266T board will run any Tualatin core, regardless of the clock speed and L2 cache size (as long as the BIOS recognises the multiplier). The only difference between the 256k and 512k chips are that the pins for SMP are not internally connected on the 256k versions.

For some reason I thought all PIII-1200 chips were ES, but I guess not.

There are some 1.26 chips listed at <A HREF="http://www.overclockers.com/" target="_new">http://www.overclockers.com/</A>.

I have an Abit ST6-RAID that I run a Celeron-1200 on as a fileserver in the office. It's been a good board - 100% stable at stock. The non-RAID version would probably o/c better. The Asus TUSL-C is another popular i815 board, but I don't think it has adjustable voltages for the Tualatin core. The newer ones might, I don't know.

- JW

 

[Unolocogringo]

Cool Thanks. I had looked there a few weeks ago and did not find any listings for the 512k models. Now i'm sure I have to have one.

I aint signing nothing!!!

 

[camieabz]

Does anyone know where the 1.4GHz 512K ones can be bought?

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[Quetzacoatl]

Hard to find outside OEM channels. I think the company that builds slimline computers have the 1.4Ghz tuallys. Maybe pricewatch or newegg...I wouldn't mind getting a 1.4 P3t myself, beats a P4 anyday (mind you, not the P4a)

"When there's a will, there's a way."

 

[mbetea]

camie-
googlegear.com has em. last time i checked though they were about $330.

I run duals because i multitask between notepad, outlook express and winamp :lol:

 

[camieabz]

Does Googlegear ship international?

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[Crashman]

They are all cross-compatable, if you have a chipset that supports Tualatins as mentioned, or a Powerleap Tualatin adapter, you can use them on most boards. The 512k gives better performance than the 256k version.

What's the frequency, Kenneth?

 

[Quetzacoatl]

Is this the same reason why the Piv northwood is soooo much better than the Piv willy? 512KB for north, and 256KB for willy, right?

In that sense, if you underclocked a P3 tually and cumine to 1.0Ghz, would the tually beat the cumine by very much because of the extar 256KB L2 cache?

Err...one more question. What is the purpose of the Motorola's 2MB L3 cache? I read something about a "backside bus". Any real usage?

"When there's a will, there's a way."

 

[jclw]

The Tualatin would beat the Coppermine not only because of the extra L2, but also because of the data pre-fetch that has been added to the core.

[Cache]---BackSideBus---[Processor]---FrontSideBus---[Northbridge]

Most new(er) processors have the L1 and L2 caches on board so they don't have a BSB anymore, only a FSB. Nearly all processors that have L3 caches nowadays have BSBs because of the high cost of including a large L3 cache on the die. Rumor has it the 0.09 micron Itanium will have a 10MB+ L3 ON DIE cache (which means it will be very expensive).

I think the P4 XEON MP chips have an on die L3 cache as well, which would help explain their price (1.6GHz = US$3600). And you thought the XEON DPs were expensive
- JW

 

[Quetzacoatl]

-Most new(er) processors have the L1 and L2 caches on board so they don't have a BSB anymore, only a FSB.
Could you explain that...

-Nearly all processors that have L3 caches nowadays have BSBs because of the high cost of including a large L3 cache on the die.
Thats a double negative =/ It would make more sense not to have an L3 cache and a bsb because it reduces the cost. I think you meant to say all processors that have L3 caches don't have bsbs because of high costs.

-Rumor has it the 0.09 micron Itanium will have a 10MB+ L3 ON DIE cache (which means it will be very expensive).
Prove it with a link. I have not heard ANYTHING about that on any of the forums

-I think the P4 XEON MP chips have an on die L3 cache as well, which would help explain their price (1.6GHz = US$3600). And you thought the XEON DPs were expensive
Prove it =/ Motorola chips don't cost that much more than the Intel and AMD fare, and they have L3 caches, 2MB in fact

You haven't even told me what the L3 cache does. Please answer the question =/

"When there's a will, there's a way."

 

[cellbiogeek]

The BSB is only for when the cache is not on the processor die (i.e. BSB is a bus on the motherboard or PCB that the processor is attached to). Thus most processors today don't have a BSB for the L1 and L2 cache.

Processors that have an L3 cashe w/o BSB would have to have the L3 cache on die which is much more expensive than having it on the mobo or the PCB the cpu is attached to.

 

[chuck232]

Here's a site and the quote:

http://www.anandtech.com/news/shownews.html?i=15766&t=an

"To push the limits even further, Madison will feature a 6MB L3 cache built on the 0.13-micron process, with a 90nm Montecito core Intel may be tempted to go beyond a 10MB on-die L3 cache. These 90nm SRAM transistors are exactly 1/2 the size of the 130nm (0.13-micron) SRAM transistors used in the 0.13-micron Northwood processors; this means that without increasing the die size of the CPU Intel would be able to outfit their desktop CPUs with a 1MB L2 cache on their 90nm process."

 

[Quetzacoatl]

NO ONE YET HAS TOLD ME WHAT THE FREAK DOES AN L3 CACHE DO?

"When there's a will, there's a way."

 

[chuck232]

Aren't all three caches the same except they have slower access times/farther away from processing unit on the chip. Therefore, L1 would be fastest and closest, L2next and then L3 last. That's probably why on P4's there's only 8K of L1 and 512 of L2. I'm not positive about this though.

 

[Quetzacoatl]

That wouldn't make much sense according to processor logic though. Every processor has a much smaller L2 cache than the L1 cahce except in the case of the Duron, which I believe has 128KB L1 and 64KB L2. Instead of an L3, wouldn't it be better to beef up the L1 and L2?

"When there's a will, there's a way."

 

[chuck232]

Probably cause it's more complicated to produce since it would have faster access times etc... Just logical thinking. And L2 cache is normally larger than L1. The faster probably the more complicated, and it probably takes up more space and so forth. Wish some guy who knew what they were talking about could help you on this one... lol

 

[camieabz]

Here's a couple of links which help to provide an explanation of L1 & L2 cache.

<A HREF="http://www.dell.com/us/en/gen/topics/power_ps4q99-L2cache.htm" target="_new">Link 1</A>

<A HREF="http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/vol6iss1_art01.pdf" target="_new">Link 2 (pdf)</A>

<A HREF="http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/cache_wp.pdf" target="_new">Link 3 (pdf)</A>

I take no responibility for any opinions formed or contradicted by these links. This is a troll free thread.

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[Quetzacoatl]

I just want to know what the [-peep-] an L3 cache will do!!

"When there's a will, there's a way."

 

[camieabz]

Ahh.

L2 cache on a motherboard used with a CPU with onboard L2 cache becomes L3 cache. Simple as that.

L3 cache sizes are usually much larger than L2 CPU cache sizes. 1MB, 2MB, 4MB etc. Known as "External level 3 (L3) backside cache".

Here's an excerpt of an Anandtech interview of Via back in 2001:

"A major problem in today's chipsets is the inherent latency associated with having to go through the North Bridge every time the CPU wants to perform a memory access. Micron has been an advocate of the use of some of the North Bridge's packaging space for integrating an on-die "L3 cache" to improve performance. What are VIA's thoughts on such an option and is it something that you may be exploring in the future?

L3 cache is just a part of the solution to reduce the CPU-memory access latency issue. The most advanced CPU bus protocols already consider the core/bus speed difference, so a split bus, out-order reply cycle, and deep outstanding bus buffer are common practices to hide the bus latency while pipelining/overlapping the CPU request cycles. So we believe that DRAM latency is not as serious an issue as most people think and that increasing memory bandwidth may have a bigger impact on overall system performance.

Having said that, however, we have to look at all possible avenues for boosting overall system performance, and believe that L3 cache is clearly a viable solution for speeding up CPU-DRAM access. We have built up strong expertise and technology for developing a cost effective L3 cache solution, but are studying the L3 cache architecture, data coherency protocol, snoop latency, and performance impact before we add an L3 cache into our chipsets."

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[Quetzacoatl]

Oh

"When there's a will, there's a way."