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Thouroughbred +1800(1.53Ghz) Overclocked to 2Ghz

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April 30, 2002 8:02:14 PM

<A HREF="http://www.vr-zone.com/#2324" target="_new">Source</A>

So is this inline with Matisaro's overclocking claims of the Thouroughbred ?

So so am I right in believing a PR +2200 Thouroughbred can be overclocked enough to achieve a PR rating of +3000 ?

<font color=purple>Ladies and Gentlemen, its...Hammer Time !</font color=purple>
April 30, 2002 8:11:01 PM

A tad low, but inline, it is probably one of the "problem" ones, but it looks sweet.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
April 30, 2002 8:25:59 PM

The way I read the text, the bugger probably managed to POST at 2.0GHz but it couldn't pass all benchmarks.

<blockquote><font size=1>Svar på:</font><hr><p>However, a clock speed of 1.9Ghz is stable passing all the benchmarks like SuperPi, Cpumark 99, SiSoft Sandra 2002, PCMark 2002 Pro and 3DMark2001.<p><hr></blockquote><p><i>/Copenhagen</i>
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April 30, 2002 8:37:35 PM

<blockquote><font size=1>Svar på:</font><hr><p>A tad low, but inline, it is probably one of the "problem" ones, but it looks sweet.<p><hr></blockquote><p>"A tad low" is the biggest understatement of the year.

I hope AMD either trash the "problem ones" or sell them OEM, so they don't end up in the hands of innocent fellow overclockers in the community.

<i>/Copenhagen</i>
April 30, 2002 8:40:45 PM

1.9ghz aircooled is not trash buddy.


Secondly, most of the bad ones will be sold as mobiles, the fact remains that chip did a 30% overlock aircooled, which is nothing to scoff at!

Thirdly, I dont blame amd for selling the low sellers as 1800+'s for the start, if you want a 2.4ghz athlon buy a 2000+ it is NOT like they are unfairly priced!!!!!

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
April 30, 2002 8:45:26 PM

200*10? Huh. Both FSB and multiplier were changed. And 2.15V is awfully high.
April 30, 2002 8:47:34 PM

Somehow I have trouble beleiving the achievement by that website's claim. It may be true, but it's not too surprising, since an AXP 0.18m was able to reach those speeds anyway.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
April 30, 2002 10:24:52 PM

How do you get 30% going from 1.53 to 1.9? Don't tell me you're using calculator on one of the original 1.13 P3s :tongue:

<font color=blue>Hi mom!</font color=blue>
May 1, 2002 12:57:27 AM

They could calculate?
Imagine Pi.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
May 1, 2002 2:16:00 AM

I went 1.5>2 thankyou very much.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 1, 2002 2:16:19 AM

three point one four one five arrrr thats close enuf eh? care for some quake? :smile:

<font color=purple>Win ME Slayer. And PROUD of it!</font color=purple>
May 1, 2002 3:10:09 AM

That can be a early sample

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May 1, 2002 11:42:39 AM

What kinda mobo and ram was used? Did the mobo have the correct divisors and was the ram able to sustain such a high frequency with stability fully retained?

It is also a very early chip. Remember how far the first Thunderbirds would go?... not even a gig.. but since then AMD improved their process. And today a 1400 can run at at least 1533 and sometimes at 1600 or more.. Not even mentioning the palomino which can do 1800 in the latest revision.. or even 1900 mhz.. or more!!!
So.. it's far too early to judge the t-bred based on the results on only one or two tests.
May 1, 2002 11:58:41 AM

I agree, these were very early samples, no Tbred is out yet, and even then, at the first week or two, the batches are not the best out there. Wait a month, then get newly fresh Tbred chips, then OC them. I guarantee an 1800+ will then reach 2700+(instead of current 2400+ unstable), which is 50% OC by PR, and therefore as challenging as FatBurger's OC. It also challenges Fugger's.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
May 1, 2002 3:44:46 PM

Considering that it's 1.53, and he couldn't even complete benchmarks at 2.0, let alone being perfectly stable...

<font color=blue>Hi mom!</font color=blue>
May 1, 2002 4:03:54 PM

I didn't say the T-Bred in general will be such a big disappointment. I agree, this is an early sample and probably not a perfect one (could even be a mobile T-bred). As I said before, I hope the "problem ones" doesn't reach the retail channels. By saying that, I'm also saying that I expect AMD to do better at launch-time or shortly after.

That said, I don't like the very moderate reduction of Vcore in T-Bred, down from 1.75V to 1.65V, compared to the P4 die-shrink Vcore reduction (1.75V -> 1.50V). That doesn't bode well in terms of clockspeed headroom and indicates that AMD used some of the clockspeed increase, which could be expected from a die-shrink, with the introduction of the Palomino core which has 0.13 micron class gate-lengths according to Intel/Matisaro. Unless AMD can dish up with some 0.09 micron class gate-length, I don't expect T-Bred will get the same kind of clockspeed increase as Northwood got.

My patience has been used up, I really can't wait more than approx. 4 weeks before making my purchase. For the moment I'm aiming for a P4 2.0A paired with an 850E or maybe an 850G (with disabled on-board graphics) depending on pricing. The lack of SSE2 in T-Bred is one of my main motivations for chosing the P4. Over time, lack of SSE2 will definately hurt.

<i>/Copenhagen</i>
May 1, 2002 8:40:52 PM

Correct me if I am wrong, but did the article not even mention what hsf they were using?

Besides, It was a sample chip most likely from the first batch, not indicitive of the tbreds overclocking ability.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 1, 2002 8:42:54 PM

Quote:
That said, I don't like the very moderate reduction of Vcore in T-Bred, down from 1.75V to 1.65V, compared to the P4 die-shrink Vcore reduction (1.75V -> 1.50V). That doesn't bode well in terms of clockspeed headroom and indicates that AMD used some of the clockspeed increase, which could be expected from a die-shrink, with the introduction of the Palomino core which has 0.13 micron class gate-lengths according to Intel/Matisaro. Unless AMD can dish up with some 0.09 micron class gate-length, I don't expect T-Bred will get the same kind of clockspeed increase as Northwood got.



It looks like 1.6 volts IIRC.

I made the argument that the extra voltage could have been used to ensure compatability.(some amd mobos cannot deliver 1.5volts to the cpu). I dont think the extra voltage bodes poorly for the overclocking ability of the chip, we will see.


:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 1, 2002 8:43:09 PM

SSE 2 is coming on ClawHammers, perfect target. IMO SSE2 was a high spot for P4, which allowed it to survive. Now CH has it, that would pretty much cripple P4 against it, if AMD uses it wisely.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
May 1, 2002 9:24:58 PM

And that's a good point, it could be the world's largest heatsink or the retail that came with the first Socket A out the door. But that doesn't change the fact that apparently 1.9 was (mostly?) stable and 2.0 was not, which is a 24% overclock.
Say, didn't you give me a link to an air-cooled 1.9 XP? Perhaps Thoroughbred doesn't overclock quite as well as people have been hoping.

BTW, the OC in the article was at 2.15v. I doubt that's safe for long periods of time, though I could be wrong. I don't know if there's a reason that the Thoroughbred would be tougher against higher voltages than the Northwood, but the <A HREF="http://www.hardforum.com/showthread.php?s=&threadid=373..." target="_new">Northwood doesn't like >2v</A>.

<font color=blue>Hi mom!</font color=blue>
May 1, 2002 9:34:24 PM

<blockquote><font size=1>Svar på:</font><hr><p>SSE 2 is coming on ClawHammers, perfect target. IMO SSE2 was a high spot for P4, which allowed it to survive. Now CH has it, that would pretty much cripple P4 against it, if AMD uses it wisely.<p><hr></blockquote><p>Yes, CH has it, but I'm not counting it in because we'll probably have to wait another half year or so before it's available to the masses.

Another thing we have to remember about SSE2 is that it depends directly on the core clock. Basically it means that the CPU with the highest core clock will benefit the most from SSE2. It is not likely that the CH will ever reach as high a core clock as the P4, so the P4 architecture will always hold the upper hand when it comes to SSE2 performance.

<i>/Copenhagen</i>
May 1, 2002 9:48:17 PM

I would just like to add that Intels claim that "Clockspeed matters" kind of makes sense, at least in terms of SSE2 performance.

<i>/Copenhagen</i>
May 1, 2002 10:52:45 PM

Intel released a paper on how % increase in PR did not match % increase in Mhz. While it was easily confusing information, and the intent was suspect, it did have a point on that aspect.

They have different starting points (Technicaly, a 0 PR would be a 466 MHZ AXP) so they don't scale equaly. An 1800+, running at 1.533 GHZ, OCed 50%, would run at 2.300 GHZ, or at PR 2950+.

This is all assuming that the T-breads are clocked and rated the same way as the current AXPs, which seems to be the case. So, you can't count your 50% increase to meet Fatburger's Challenge by PR rating.

I want to be your Opteron... Why don't you call my name - Peter Gabriel?
May 1, 2002 11:00:55 PM

Quote:
BTW, the OC in the article was at 2.15v. I doubt that's safe for long periods of time, though I could be wrong. I don't know if there's a reason that the Thoroughbred would be tougher against higher voltages than the Northwood, but the Northwood doesn't like >2v.


Thats another good point, for all we know they set it at 2.15 right off the bat and saw how far they could crank it up, but the ultra high voltage may have been causing waay to much heat for a stable overclock, many times(especially with smaller processes) you do not need a big overvolt for stability, and going too far causes your topspeed to actually lower.

So that report leaves alot to be desired.

However I will say this, very rare were the xp's which would do 1.9aircooled, and if one of the very first tbreds off the line can do 1.9 aircooled(under unknown circumstances) I would take that as a good sign!.

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May 1, 2002 11:01:54 PM

Quote:
Another thing we have to remember about SSE2 is that it depends directly on the core clock. Basically it means that the CPU with the highest core clock will benefit the most from SSE2. It is not likely that the CH will ever reach as high a core clock as the P4, so the P4 architecture will always hold the upper hand when it comes to SSE2 performance.


Where did you hear that?

Links?

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 1, 2002 11:25:41 PM

Quote:
Thats another good point, for all we know they set it at 2.15 right off the bat and saw how far they could crank it up, but the ultra high voltage may have been causing waay to much heat for a stable overclock, many times(especially with smaller processes) you do not need a big overvolt for stability, and going too far causes your topspeed to actually lower.


I'd be surprised if they did something that stupid, but it's possible.

<font color=blue>Hi mom!</font color=blue>
May 2, 2002 12:18:24 AM

Yes I was about to comment on Copenhagen's claim.
I recall somewhere reading SSE2 would benefit more if it was taken off the P4 FPU, into the ALUs once running 32-bit, and thus benefit further. The idea of clock speed only sounds rather ridiculous, I mean why would it be better if its job is to make the cycles less to execute multimedia content! I would say equal IPC and MHZ would make the improvement with SSE 2 much better, than just MHZ. That would explain why some SSE2 benchs showed the Athlon STILL competing well against P4s.
Also Copenhagen said we'd wait a year for SSE2 support. First of all why should it be different than Intel's? They are the ones licensing it to AMD, right? So AMD uses the same set in it or they might remove some, but anyway we currently have a good amount of SSE2 supporting apps, which means CH will benefit right out of the box from them, than when P4 came out.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
May 2, 2002 5:29:47 AM

Quote:
'd be surprised if they did something that stupid, but it's possible.


Actually you would be surprised at the number of people who AUTOMATICALLY up their core voltage to 1.85 before they EVEN START overclocking.

Many hardcore ocers dont understand why higher voltage could possibly be a bad thing.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 2, 2002 7:32:19 AM

I can almost feel the "I told you so" comming...
we may dont know much - but from what we do SEEM to know - 24% stable OCing with high voltage, it does not look as if T-bred is going to OC as well as the NW in %.


This post is best viewed with common sense enabled
May 2, 2002 7:57:47 AM

No IIb, we dont really know anything, wait for the actual chips to come out and for us to get a more comprehensive cross section of cores before making any judgements.



:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 2, 2002 11:57:02 AM

Yeah, I mean right now we got about 3 reasons the results are flawed or not too indicative of true OCability. If anything they are degrading Tbred's appeal.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
May 2, 2002 2:02:04 PM

<blockquote><font size=1>Svar på:</font><hr><p>Where did you hear that?

Links?
<p><hr></blockquote><p>That should be common knowledge. You can read it a lot of places. I'll just give you the below quote and then a link.

<i><font color=blue>SSE is a single instruction multiple data (SIMD) processing scheme. SIMD combines several intensive computations into a single instruction. <b>The single instruction can then be processed in as little as one CPU clock cycle</b>, thus allowing for much improved performance over traditional core operations.</i></font color=blue>

<A HREF="http://www.sysopt.com/articles/p4/index2.html" target="_new">http://www.sysopt.com/articles/p4/index2.html&lt;/A>

Read the paragraph: "Multimedia Register Extensions"


<i>/Copenhagen - Clockspeed will make the difference in the end</i>
May 2, 2002 3:32:01 PM

Quote:
That should be common knowledge. You can read it a lot of places. I'll just give you the below quote and then a link.

Trouble with that theory is that a single clock cycle is by no means the smallest unit of CPU time. Processors as early as the Pentium classic were in some cases able to execute some instructions in less than one clock cycle, due to parallel processing within the CPU core. The P6 core (PPro, PII, and above) split it even further; instead of just clock cycles, instruction overhead is also measured in discrete micro-ops. The Hammer could easily do the same thing and thus perform SSE2 as fast as a P4 at a lower clockspeed.

In fact, the Palomino already did as much with SSE when it was released (SSE2 is really just an expansion of SSE). See these <A HREF="http://www.aceshardware.com/Spades/read.php?article_id=..." target="_new">ancient KribiBench results</A> to see how well the Palomino did at SSE, even with a 500MHz handicap. Apparently clockspeed is not the all-determining factor with SSE; why should it be so with SSE2?

<i>If a server crashes in a server farm and no one pings it, does it still cost four figures to fix?
May 2, 2002 3:45:25 PM

I know, but most people like that aren't the ones that AMD would trust an engineering sample to, either.

<font color=blue>Hi mom!</font color=blue>
May 2, 2002 6:00:46 PM

<blockquote><font size=1>Svar på:</font><hr><p>Trouble with that theory is that a single clock cycle is by no means the smallest unit of CPU time. <p><hr></blockquote><p>No, but in relation to SSE2 it is, at least for the time being, maybe CH will change that, but I doubt.

As far as the Athlon's SSE2 performance goes, you must remember that not all code can be written as SSE2 instructions, and every time it doesn't the Athlon will benefit from it's general higher FPU efficiency and IPC. It really depends on how well the code is optimized and how well the application suits the instruction set.

<i>/Copenhagen - Clockspeed will make the difference in the end</i>
May 2, 2002 6:55:33 PM

ALU, AGU and FPU execution units also make calculations at 1 clock cycle. but this is not to say processor preformance is totaly dependent of clockspeed and the number of its execution units.

for example a high pipline stage count processor might work fater (in Mhz) but sence it miss-predects more often and the penlty for miss prediction is great then he might be working at higher clockspeed but not necesrly keeping its execution units filled (x86/87 or SIMD) at better effency.

there are many things impacting the processor ability to keep its execution units filled... BUS speed, Cahche architecture, branch predection etc... as all instruction SIMD also must go through all partes of processing before it is executed. the execution though is 1 clockcycle.


This post is best viewed with common sense enabled<P ID="edit"><FONT SIZE=-1><EM>Edited by iib on 05/02/02 09:59 PM.</EM></FONT></P>
May 2, 2002 8:10:23 PM

So in general, the CH's usage of multimedia will be better. Since you got either way backing up the needed instruction use, so if SSE2 won't cut it, call in the FPU, and when the latter won't, go for SSE2! I wonder where they placed the set on what core component.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
May 2, 2002 8:28:09 PM

<blockquote><font size=1>Svar på:</font><hr><p>So in general, the CH's usage of multimedia will be better.<p><hr></blockquote><p>Yes, if CH debuts with the same clockspeed as the NW will have at that time, but that won't happen. I recall CH will debut at around 2.0GHz while P4 will be running around 3.0GHz. We'll probably see P4 taking the lead in applications extremly well suited and optimized for SSE2, while CH could dominate applications which are only medium suited for SSE2 and totally dominate all other non-SSE2 optimized applications.

<i>/Copenhagen - Clockspeed will make the difference in the end</i>
May 2, 2002 8:51:15 PM

Quote:

Yes, if CH debuts with the same clockspeed as the NW will have at that time

not nececerly:

Quote:

ALU, AGU and FPU execution units also make calculations at 1 clock cycle. but this is not to say processor preformance is totaly dependent of clockspeed and the number of its execution units.

for example a high pipline stage count processor might work fater (in Mhz) but sence it miss-predects more often and the penlty for miss prediction is great then he might be working at higher clockspeed but not necesrly keeping its execution units filled (x86/87 or SIMD) at better effency.

there are many things impacting the processor ability to keep its execution units filled... BUS speed, Cahche architecture, branch predection etc... as all instruction SIMD also must go through all partes of processing before it is executed. the execution though is 1 clockcycle.

This post is best viewed with common sense enabled
May 2, 2002 11:19:37 PM

Quote:
As far as the Athlon's SSE2 performance goes, you must remember that not all code can be written as SSE2 instructions, and every time it doesn't the Athlon will benefit from it's general higher FPU efficiency and IPC. It really depends on how well the code is optimized and how well the application suits the instruction set.


Copenhagen, sse and sse2 performance is not dependant on clockspeed, just because the p4 runs at 3ghz does not mean that the clawhammer at 2ghz will perform sse2 functions slower than the p4.(it may but it is not certain it will).


As kelledin stated there are many ways amd can tweak its sse2 engine to perform better, just like they did with sse1(the sse1 performance of the athlon is better than the p3/p4 at even lower clockspeeds).

Your link does not state that sse2 performance is directly linked to purely clockspeed, so please again, I ask where did you hear sse2's performance is DIRECTLY LINKED to the cores clockspeed.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 3, 2002 7:12:17 PM

<blockquote><font size=1>Svar på:</font><hr><p>Your link does not state that sse2 performance is directly linked to purely clockspeed, so please again, I ask where did you hear sse2's performance is DIRECTLY LINKED to the cores clockspeed.<p><hr></blockquote><p>The link I provided will do. Unfortunately not everything here in life is black and white, often there is something in between. What article says is basically that the execution of a SSE2 instruction can be completed in as little as one clock-cycle. Taken to the extreme: If you have an application which is written using SSE2 instructions only (not very likely), each programline can be executed in one clock-cycle. The execution speed of this application will hence be DIRECTLY LINKED to the clockspeed of the core. It is therefore a perfectly valid statement to claim that <b>SSE2 performance</b> depends directly on the core clock.

But as real life applications cannot be and is not solely made out of SSE2 instructions the outcome is no longer black or white, but something in between. Applications in which the main task consists of calculations which takes place on a small set of data at the time with intensive SSE2 usage, will almost scale proportional to the core frequency. I'm confident that we are going to see a number of applications that are extremly well SSE2 suited and optimized. In these applications a P4 @ 3.0GHz will scream past a CH @ 2.0GHz. There will be other applications that ARE SSE2 optimized, but where large and frequently used parts of the code cannot be implemented with extensive usage of SSE2. Most likely a CH @ 2.0GHz will dominate a P4 @ 3.0GHz. If that application is Microsoft Word, I won't mind. :wink:

<i>/Copenhagen - Clockspeed will make the difference... in the end</i> :cool:
May 3, 2002 7:17:59 PM

Quote:
What article says is basically that the execution of a SSE2 instruction can be completed in as little as one clock-cycle. Taken to the extreme: If you have an application which is written using SSE2 instructions only (not very likely), each programline can be executed in one clock-cycle. The execution speed of this application will hence be DIRECTLY LINKED to the clockspeed of the core. It is therefore a perfectly valid statement to claim that SSE2 performance depends directly on the core clock.


ON THE P4, this does not state that sse2 ITSELF, increases purely due to clockspeed, nor does it say the p4's sse2 excecution core is the only way to run sse2, so your statement is in fact wrong as I said.

Thanks for the linkage though.


Quote:
It is therefore a perfectly valid statement to claim that SSE2 performance depends directly on the core clock.


It is valid to say that the p4's sse2 performance is directly related to clockspeed(it really isnt but that statement has some truth) but it is NOT valid to say hammers sse2 will be slower than the p4's cause it has a slowerclockspeed. The hammers implimentation may/will be different, and your links did NOT state that sse2 ITSELF is dependant on core speed, only the p4's sse2 engine!

plain and SIMPLE.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 3, 2002 7:20:06 PM

Quote:
But as real life applications cannot be and is not solely made out of SSE2 instructions the outcome is no longer black or white


Heres one to think about.

Why would amd enable sse2 support which would ENSURE it ran slower than a faster p4, when it has the excecution engine to do sse2 code faster than the p4(as evidenced by the athlon winning sse2 benchmarks).


You can bet your ASS amd will not include sse2 support which is slower than the clawhammer can run nativly WHAT WOULD BE THE POINT?


:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 3, 2002 7:40:23 PM

<blockquote><font size=1>Svar på:</font><hr><p>and your links did NOT state that sse2 ITSELF is dependant on core speed, only the p4's sse2 engine!<p><hr></blockquote><p>Yes, I know, as SSE2 is an Intel specification and was made for P4. Others could implement it differently, but we don't know that at the moment, I can only provide links to something that is for real, not to something that isn't known and availble yet.


<i>/Copenhagen - Clockspeed will make the difference... in the end</i> :cool:
May 3, 2002 7:43:34 PM

<blockquote><font size=1>Svar på:</font><hr><p>You can bet your ASS amd will not include sse2 support which is slower than the clawhammer can run nativly WHAT WOULD BE THE POINT?<p><hr></blockquote><p>Quite simple: Marketing.

Intel has hyped SSE2 for quite a while now and it's slowly becoming a feature that people want.


<i>/Copenhagen - Clockspeed will make the difference... in the end</i> :cool:
May 3, 2002 8:19:24 PM

I totally forgot about how SSE on Athlon is competitive to SSE2 optimized apps on P4. This would maybe signify that since the SSE2 adds to SSE instructions, that the Athlon or CH would scream even further, showing that the P4 at 3GHZ will not necessarily destroy the crap out of it.

--
Thunderbirds in wintertime, Northwoods in summertime! :lol: 
May 3, 2002 8:30:19 PM

Quote:
Yes, I know, as SSE2 is an Intel specification and was made for P4. Others could implement it differently, but we don't know that at the moment, I can only provide links to something that is for real, not to something that isn't known and availble yet.



You said sse2 itself, NOT the sse2 engine in the p4, sse2 itself is NOT dependant on clockspeed purely, and can be done in many different ways, period.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 3, 2002 8:32:12 PM

Quote:
Quite simple: Marketing.

Intel has hyped SSE2 for quite a while now and it's slowly becoming a feature that people want.


Just like sse on the axp was just an empty marketing tool, oh wait, the axps sse WAS BETTER THAN intels! AMD does not cripple its chips for marketing, and I challenge you to give me one instance in which that has happened.

The hammer will have sse2, and you can bet good money that it will be functional, and not GUARENTEE a loss to a higherclocked p4 in sse2 apps.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
May 3, 2002 8:56:03 PM

The Athlon XP's SSE has one more instruction than the P3's SSE. Most people don't realize that, and it partially explains that difference you're talking about.

(Not really saying that to you, just in general)

<font color=blue>Hi mom!</font color=blue>
May 3, 2002 10:06:05 PM

<blockquote><font size=1>Svar på:</font><hr><p>You said sse2 itself, NOT the sse2 engine in the p4, sse2 itself is NOT dependant on clockspeed purely, and can be done in many different ways, period.<p><hr></blockquote><p>Lets get one thing straight: Currently the P4 is the ONLY CPU which has SSE2. It's is thus natural that any discussion about SSE2 implementation must revolve about the current reality, until we see something else.

As I've said earlier (and I'm starting to get borred by saying it multiple times), what will save AMD's butt is CH's general high IPC and the fact that not all applications can be implemented based entirely on SSE2. Some applications will probably perform better on CH even if they're SSE2 optimized, because large and frequently used portions of the program needs to do other stuff that can't be done using SSE2. But I'm also sure that a P4 3.0GHz P4 will SCREAM past a 2.0GHz CH in other SSE2 intensive apps.


<i>/Copenhagen - Clockspeed will make the difference... in the end</i> :cool:
!