Question about AMD Bus Speeds

[Poritz]

I thought that the current line of AMD CPUs have a 266Mhz bus but now I am hearing that it is 133Mhz and that they do not want to move up to 166Mhz. Can someone explain and point me to some place that can give me an introduction to modern PC architecture so that I may better understand. Thanks, I look forward to hearing from someone soon.

Poritz

 

[baldurga]

No problem. In fact they run at 133Mhz, but memory because its DDR, can transmit information in the raising and the falling of each cycle, doubling in fact the velocity. For this reason they talk about 266Mhz (for memory) and 133Mhz (for FSB).

Now, if AMD FSB moves to 166Mhz, you cuold take more advantage for 333Mhz Memory (166 x 2 because is DDR), because it will work sincro. Currently there are chipsets that support 166/333 (like KT333).

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[Matisaro]

Good explination, you forgot the fact that the system bus itself is also ddr, so thew 133fsb is 266 actual(133x2).

Even if the ram is sdr(single data rate) the athlons bus is still double pumped.

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[Poritz]

Thanks I appreciate the response. Is there a place where I can read something more indepth?

Poritz

 

[eden]

Read the name of the website you are at now.
Or head to Anandtech.com

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[texas_techie]

"HyperTransport devices are designed to operate at multiple clock speeds up to 800 MHz, transferring two bits of data per clock cycle, for an effective transfer rate of 1600 Mb/sec in each direction"

So a really interesting question is at what speed will the CH bus be at. Since the official spec says "UP TO" 800mhz.

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[baldurga]

Thanks Matisaro!

In fact, there is something that I want to know and problably you have the answer. It's correct to say:

a) the information runs at 266Mhz between memory(DDR) and chipset
b) the information runs at 266Mhz between chipset and CPU (AMD Tbird or XP)
c) BUT CPU is clock at 133 times the multiplier.

If this is right, am I wrong assuming the procesor gets twice the information it's clock, but because of the multiplier (making let's say 1.2Ghz) can "absorb" this 266Mhz? So, AMD calculates that the "optimum feeding" for it's processors is 266Mhz?

A little more deeply: if there is a "optimal ratio" between CPU Mhz/FSB Mhz (the one that feed CPU with just the data that can process, nothing more and nothing less) shouldn't be diferent for every CPU? Because a 1.2Ghz CPU can't "assimilate" as many data as a 1.6Ghz CPU, the FSB should be lower than the higher clocked CPU.

I assume that this optimal is just theoric and may change between programs that requieres diferent operations, but seems reasonable. What's more, what is the value of this ratio?

I hope I haven't bored you will all this thinking/meditation.

I have adressed the questin to Matisaro, but obviously anyone is welcome to help me.

Thanks in advance!

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[Matisaro]

If this is right, am I wrong assuming the procesor gets twice the information it's clock, but because of the multiplier (making let's say 1.2Ghz) can "absorb" this 266Mhz? So, AMD calculates that the "optimum feeding" for it's processors is 266Mhz?

The cpu isnt constantly recieving data(it can be but most times it isnt), the cache plays a large role in what kind of data access the cpu recieves, but your right, the ddr sends data to the cpu via the 266 bus, and sometimes the cpu dosent need data, and other times it needs it faster, its controled by the cpu.

Thats where latency comes in, if the cpu needs data, but its not in its cache, it has to ask the system memory for it, and depending on your setup this can take upto 100ns and during that time the cpu usually is idle, so while a faster bus can be good, a lower latency bus can be good too.

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[Matisaro]

BTW, i took 3 vicadin so my posts may not be coherant right about now.

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[FatBurger]

And I see you hit Forum Fixture, congrats. What's the Vicadin for?

BTW, I was thinking about effective clock speeds a while ago. If clock speed was measured using the effective clock speeds instead of real clock speeds, think of the difference. The P3 wouldn't change, the Athlon's clock speed would double, and the latest P4s would be running at just over 10GHz. That'd make their IPC even lower than it is the traditional way.
Sort of a pointless thought, but something that struck me.

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[Matisaro]

Toothache, woo hoo forum fixture.

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[baldurga]

Thanks again Matisaro! And no, your post was OK, now I have a little bit more knowledge than before.

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