AMD is putting out three chips for the chipsets on the mainboard. The PCI-X bus, The hypertrans I/O bus, And the AGP 8x tunnel.
After looking at the Hypertransport consortium's website - I see the max bit rate across the bus is 32 (32 bit). So im at a loss to see how graphics can benefit, at least from a bit size perspective. Now we all know that H.T. is REAL fast, but again were at looking at bit size not speed.
BUT:
"PCI-X, at 133 MHz and 64-bits, will enable data throughput of over 1 Gbyte/sec."
So apparently HT can only do 32-bit. But PCI-X can handle 64-bit. But im still confused as hell. How does the pci-x tunnels (supporting up to 5 pci masters) work with the I/O hub (aka the southbridge of a hammer chipset)? The specs for each chip all show diff bit-size support.
Only thing i understood from my researchwas the AGP tunnel chip is necessary so that graphics cards can operate on a HT setup.
Anyone actually know how all this crap fits together? Im too lazy to go tap my sources...
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