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Hammer with 1MB L2 Cache!!!

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June 4, 2002 7:26:12 PM

Hey guys I just read the article about Computex Day 2 At <A HREF="http://www.anandtech.com/showdoc.html?i=1632&p=5" target="_new">Anandtech.com</A> and according to him the hammer has 1MB of L2 Cache. Also one big disappointment is that it's only running at 800Mhz.

Anyways, Wasn't the Hammer suppose to have only 512Kb of L2 cache. Do you know if AMD will keep the 1MB and release Claw with 1MB?

KG

"640K ought to be enough for anybody." - Bill Gates.

More about : hammer 1mb cache

June 4, 2002 11:03:00 PM

1Mb (small 'b' for bits) will probably be for Opteron, and 512k for Clawhammer. Also, HardOCP noted that the 800MHz chips were just samples so that mobo makers could have working parts, they weren't for benchmarking purposes. That shouldn't be indicative of the release clockspeed in any way.

<font color=blue>Hi mom!</font color=blue>
June 4, 2002 11:11:08 PM

Yes, the Opteron will only have up to 1Mb of cache, while the "Athlon 64" will supposedly have up to 512kb, although I've heard it may only be 256kb.
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June 4, 2002 11:59:48 PM

How can it be only 256kb since the Barton which will be releasing before Hammer will have 512kb. Hammer should atleat have 512. I think 256kb will lower the preformance rating big time.

KG

"Artificial intelligence is no match for natural stupidity." - Sarah Chambers
June 5, 2002 1:07:34 AM

Quote:
1Mb (small 'b' for bits) will probably be for Opteron, and 512k for Clawhammer.

Huh? It's 1 MB, or megabyte, of L2 cache on Opteron. 1 Mb = 128 KB, which is way too small.

Ritesh
June 5, 2002 2:13:03 AM

The info fairy sprinkled her magic dust on me....

It is possible that the CH - athlon 64 - whatever will have 1 Mb L2.. but its not definite. The fairy also said the extra cache makes a pretty big difference.

Benchmarks are like sex, everybody loves doing it, everybody thinks they are good at it.
June 5, 2002 2:16:30 AM

penguin.


<i>if <b>you know</b> <font color=white>you don't know<font color=black>, the way could be more easy ...
June 5, 2002 2:17:01 AM

Well you did say they were toying with cash.
Although it's that new mysterious technology you said about, which I hope the fairy will visit you with!
Anyway it's nice to see more ways to make CH a definite competition, I hope.

--
Meow
June 5, 2002 5:03:55 AM

I hope so too Eden.. im wondering what the heck it is myself. I have only heard it refered to by name, not by what it does :( 

Benchmarks are like sex, everybody loves doing it, everybody thinks they are good at it.
June 5, 2002 7:30:58 AM

Quote:
1Mb (small 'b' for bits) will probably be for Opteron, and 512k for Clawhammer. Also, HardOCP noted that the 800MHz chips were just samples so that mobo makers could have working parts, they weren't for benchmarking purposes. That shouldn't be indicative of the release clockspeed in any way.



Amd representitives told the inquirer that the samples were locked at 800mhz to prevent motherboard makers from overclocking them and giving people expectations they could not possibly keep up with.


That leads me to believe they will release the hammer with ubar headroom, thats what I got from the statement anyways.


However with no fsb or multiplier, I dont know if we will be able to overclock said hammer AT ALL, we will see.

:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
June 5, 2002 7:31:54 AM

whats the name, pm me with it.




:wink: The Cash Left In My Pocket,The BEST Benchmark :wink:
June 5, 2002 11:55:28 AM

Well like I was suggesting, it might be a direct clock speed OC. Maybe it goes in sync with the bus, so both go up as you up the speed. Although there is no bus anyway, cuz if there was, one that runs at 2GHZ would've given Hammer a HUGE performance increase. This ain't no 400->533MHZ jump people! This would be a 266->~2GHZ!

--
Meow
June 5, 2002 6:26:09 PM

Quote:
<i>ritesh_laud says:</i>
Huh? It's 1 MB, or megabyte, of L2 cache on Opteron. 1 Mb = 128 KB, which is way too small.


Cache is always measured in bits. The Northwood has 512kb of L2, the Athlon has 256kb of L2, etc.

Quote:
<i>Eden says:</i>
Well you did say they were toying with cash.


Shouldn't they be spending it on research?

Quote:
<i>texas_techie says:</i>
I have only heard it refered to by name


And I bet it's another Transformers name, too. I've got $5 on Metaron.

Quote:
<i>Matisaro says:</i>
That leads me to believe they will release the hammer with ubar headroom


That could very well be. I'd question that strategy, though. AMD needs to make a huge release, they can't afford to have people either slightly disappointed or just kind of satisfied at the beginning, then ramp up to better performance, regardless of how fast they do it.
People hate the P4 too much for them to do something sort of similar (not to the same extreme, of course).

Quote:
<i>Eden says:</i>
Well like I was suggesting, it might be a direct clock speed OC.


I agree. I see no reason why the IHS or the disappearing of the FSB/multiplier relationship means there will be no more overclocking. If there's a clock, it can be changed, pretty much. Whether AMD leaves that option open is another story, but I see no reason that it would be technologically impossible to overclock.

Quote:
<i>Eden says:</i>
This would be a 266->~2GHZ!


Difference being that the RAM wouldn't be running at quite that speed. But it should still make a difference.

<font color=blue>Hi mom!</font color=blue>
June 5, 2002 8:19:27 PM

I meant cache, sorry.

BTW since when is bits for cache? I always, always heard it as kilobytes. Bits would be way too poor, I mean P4s have 1 kilobyte of cache??? ew.

--
Meow<P ID="edit"><FONT SIZE=-1><EM>Edited by Eden on 06/05/02 04:20 PM.</EM></FONT></P>
June 5, 2002 8:28:41 PM

No FSB?

Just because the memory controler is in the chip doesn't mean that the Bios can't adjust the FSB.

"Search your feelings you know it to be true, I am your... twin sister" - Darth Vader
June 5, 2002 8:39:12 PM

Change the Core To Memory Devider?


This post is best viewed with common sense enabled
June 5, 2002 8:45:06 PM

it is bytes...

This post is best viewed with common sense enabled
June 5, 2002 9:00:24 PM

Yeah I thought so too, I wonder how it could be bits, it's way too small...

--
Meow
June 5, 2002 11:35:56 PM

Quote:
<i>Eden says:</i>
I meant cache, sorry.

I know, just too good of an oppurtunity to pass up.

Quote:
<i>Eden says:</i>
BTW since when is bits for cache? I always, always heard it as kilobytes. Bits would be way too poor, I mean P4s have 1 kilobyte of cache??? ew.

Well, paint me pink and call me "penguin". It is bytes :redface:

<font color=blue>Hi mom!</font color=blue><P ID="edit"><FONT SIZE=-1><EM>Edited by FatBurger on 06/06/02 10:43 AM.</EM></FONT></P>
June 5, 2002 11:44:12 PM

Umm, it IS KB. Refer to this article:

<A HREF="http://athlonxp.amd.com/technicalInformation/" target="_new">http://athlonxp.amd.com/technicalInformation/&lt;/A>

You confused me when you used kb. In my post, change all the numbers to KB, then they make sense. Well, if "Athlon 64" (clawhammer) does have 512KB , it will cost a bit more than usual, I believe. Opteron will ahve up to 1MB, but I believe it's core will be larger than claw with the max amount of cache. And since AMD wants to keep the core as small as possible (smaller then Tbred) for the clawhammer, I wonder where they can possibly find the space to insert extra cache and support their claim of the really small core.
June 6, 2002 1:46:14 AM

The core of CPUs is actually very small. Someone "in the know" said less than 10% of the silicon is core, the rest is cache.
Course whoever told me that could have been retarded too.

Benchmarks are like sex, everybody loves doing it, everybody thinks they are good at it.
June 6, 2002 1:53:10 AM

Well, not according to any of my knowledge. I guess I could go and dig up some pics of some cut-open AXP's and P4"s to show that cache covers alot less than 90%. Now, unless I can be proven otherwise, cache doesn't take that much space. I'll try and post the pic links as soon as I find them.
June 6, 2002 3:04:45 AM

from what ive seen/heard 25% is core logic the other 75% is "cache-like" structures....meaning TLB(virtual -> physical address lookup table), BTB (branch prediction), and L1 cache. but what does this have to do with the post?

ive had to design a pipelined processor for a class before...it was a lot of debugging but much less logic involved than you would think, mostly registers and ROMs, besides the ALU of course.
June 6, 2002 3:22:55 AM

Well...

Let's assume that the transistor count for cache is approximately linear to the cache size. This is a rough approximation, since of course there's also the control logic et al. But it's probably sufficient, as the cache size itself is the major contributing factor.

Let's also assume that the transistor count is the major factor in wafer area consumed. Also a rough approximation.

The <A HREF="http://www.extremetech.com/article/0,3396,s=1005&a=2070..." target="_new">Willamette->Northwood transition</A> added 13 million transistors, mainly for 256K extra cache (42 million transistors upped to 55 million transistors).

In a <A HREF="http://www.anandtech.com/showdoc.html?i=1261&p=2" target="_new">T-bird-vs-Spitfire comparison</A>, the advantage of 12 million more transistors seems to account for 192K of cache. It's obviously a good idea to go with AMD's "cache factor," which is ~62500 transistors per 1K of cache.

1MB (1024K) of cache = 62500*1024 = 64 million transistors for 1MB of L2 cache, assuming AMD stays with the same cache technology from the current Athlon. Also, assuming the L1 cache uses the same technology (doubtful, but let's assume for a point of reference), that's another 8 million transistors for 128K of L1, for 72 million transistors.

While AMD is going all slap-happy with the L2 cache, they might double the L1 cache as well. That might make for another 8 million transistors, for a possible total of <b>80 million transistors</b> for L1 and L2 cache combined. Ouch!

<pre>We now <b>return</b>(<font color=blue>-1</font color=blue>) to an irregular program scheduler.</pre><p>
June 6, 2002 6:37:04 AM

Cache also is very actie part of the CPU and is a significant contributer to heat. This means you cant just slap extra cache on the side as it will create a hot spot on the CPU. It is all a very tricky business.

<font color=blue> The Opteration was a success... I'm now a full-wit</font color=blue> :eek: 
June 6, 2002 5:46:11 PM

Quote:
<i>Dark_Archonis says:</i>
Umm, it IS KB.


Yeah, I fixed the post above yours, so it should make sense now.

Quote:
<i>texas_techie says:</i>
Someone "in the know" said less than 10% of the silicon is core, the rest is cache.


Anandtech has a couple of core images showing what's where and how much space it takes up. I think the core is more than 10%, but it's still the smallest amount of it.

Quote:
<i>phelk says:</i>
Cache also is very actie part of the CPU and is a significant contributer to heat.


Which is part of the reason that the 300A was a good overclocker. It had less cache.

<font color=blue>Hi mom!</font color=blue>
!