Although I doubt many will know this really, let us say you look at a table showing the Hammer speccs, compared to K7. The IPC for a Palomino is saying 9, P4 has 7. Would it be safe to assume Hammer's will say above 10?
Also with such IPC and non-requiring high insane clock speeds, can bandwidth issues still appear, such as the need to use higher than PC2700, at say 2GHZ, even as Athlons can still work well under PC2100 and 266MHZ FSB at such speeds?
It is my feeling that increasing the amount of instructions completed per clock cycle would necessarily require a corresponding increase in memory/CPU bandwidth requirements for ideal operation. The thing is we haven't been close to ideal operation for quite a while now. Now we merely claw and kick our way to any small increase in said bandwidth we can get to compliment what we know we will get on the CPU performance side as a result of Moores law.
Yeah logically that makes sense. They indeed beat the disadvantage a bigger pipeline brings. Assuming it had 10 stages, the IPC would have been 20% higher than the current one too!
I just can't wait to see 1.6GHZ+ samples, with 512K L2 cache. Indeed if that website was right, then Clawhammer might just be AMD's new flagship, and that it won't have put all its eggs in the basket carrying a huge risk, as Slvr once stated. (though not exactly like that)
Let us hope the CH carries such an improvement in the end, and its price will be justifyiable. BTW according to the website's results, it had a big ~50% improvement over the MP 800MHZ (Palomino core?), and also without the 512K cache. It might just mean that the CH could up the average IPC increase up to 40% from there! Let us hope though, it would be well enough to compete the latest Intel by then, and I think that would bring a very nice competition to the market, and indeed a product that would ressemble the upgrading from 286 to 386 times as some said. I can only imagine MPeg 4 encoding, and Lightwave 7B benchs, WITH SSE 2 too!