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Hammer - dually boards and Sun

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June 14, 2002 6:03:23 PM

Two topics in one - Sun using Hammers and a report of a dually board.

First off, the <A HREF="http://www.theinquirer.net/20050203.htm" target="_new">Inquirer</A> is reporting that Sun will start using Hammer in a smaller server line. This would help AMD tremendously, both in sales and reputation. They wil struggle to get as good a reputation as Intel in the midsize server market, let alone the big players in the large server market. Sun's support and influence would be a huge help.


The Inquirer is also reporting a <A HREF="http://www.theinquirer.net/18050202.htm" target="_new">dually board</A> that was seen for Hammer. Not much is known, but some interesting things stuck out for me when I saw the picture:

Blank header: Above the CPU on the right, there are traces to what almost looks like an IDE header, just below the PCI slots. Maybe placement for a CNR slot?

RAM banks: There's a crapload of them. Probably just testing for maximum stability with lots of DIMMs, but I wonder how many will find their way onto retail boards. Also, since there are two "channels", you'll need a minimum of two sticks. Do both CPUs need the same amount of RAM? It could cause some interesting scenarios if not, but nothing serious.

Power: There seems to be an awful lot of power regulation going on. Looks like the Hammer is a pretty complex platform, I wonder how that will effect both prices and smaller mobo makers producing motherboards for Hammer. We might see very expensive, but very good motherboards coming out.


I just noticed something odd. Is it me, or are there 8 DIMM slots on the left and 9 on the right? Both banks have two sticks apparently, but it looks like there is a different number of slots. Interesting.


This is just a test board, so it's not completely indicative of what retail (or even reference) boards will look like. It's also probably just the 800MHz samples of Hammer sitting on there.

<font color=blue>Hi mom!</font color=blue>
June 14, 2002 10:02:49 PM

ah ha! gabby! i know that dude from a gL1 forum, damn, he always said he was involved, but i didn't think that high up. good going gabriele! test board or not, i would love to see retail boards keep the same layout for the cpus at least. theres definitely a heat issue with the current mp/mpx boards with the cpu 1 placement.

[insert philosophical statement here]
Anonymous
a b à CPUs
June 14, 2002 10:18:01 PM

LoL
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June 14, 2002 10:24:11 PM

Cool.
June 15, 2002 3:44:27 AM

Nice spotting.

I was thinking that the blank header is either a test point, or a good place to put a HyperTransport Connector (Have they released a spec for that yet?).

The RAM banks may or may not have equal numbers of slots; they're obscured towards the end so it's hard to tell - that's if they can indeed have differring amounts of RAM per CPU. Or the case was off to they swap some RAM out when they took the pic... :-)

I think the Hammer platform is pretty sensible, when compared to the current SMP designs. Each CPU can get max bandwidth to its RAM, as opposed to P4 where it's a shared bus, or Athlon where it's shared from the NB. It should scale up nicely too, I think.

<i>Do I look like I care?</i>
June 15, 2002 8:33:17 AM

It's 6 on the right and 8 on the left as far as I can tell.

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June 15, 2002 8:37:22 AM

Whoops, didn't see the bigger picture of it. It's 8 and 8 now hehe.

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June 15, 2002 2:26:32 PM

jesus man, how many of you guys wear coke-bottles? i didn't think the pic was that difficult to see.

[insert philosophical statement here]
June 17, 2002 5:38:40 PM

Quote:
<i>poorboy says:</i>
I was thinking that the blank header is either a test point, or a good place to put a HyperTransport Connector (Have they released a spec for that yet?).


Hypertransport is for use internally, I haven't heard of any plans to use it as a USB-type interface.

Quote:
<i>poorboy says:</i>
The RAM banks may or may not have equal numbers of slots;


I miscounted, they're equal.

Quote:
<i>poorboy says:</i>
I think the Hammer platform is pretty sensible, when compared to the current SMP designs.


I agree, but I don't know much of it from a low level. I'd love to hear how programming for it will be, whether there will be optimizations that can be made for the way the platform works, or if it'll basically stay the same, or...

<font color=blue>Hi mom!</font color=blue>
June 17, 2002 7:41:59 PM

It looks like 9 but I think that the "9th" is something on the motherboard. If it were another DIMM clip it would be up like the rest and not down. Just an optical illusion.

Dual, 4-way, and 8-way Hammer platforms all use 8 DIMMs for each processor. So I highly doubt that it is a "9th."

<b>"Sometimes you can't hear me because I'm talking in parenthesis" - Steven Wright</b> :lol: 
June 17, 2002 9:52:24 PM

Yeah, it was 8 - A trick of the light there...

HyperTransport is designed for PCB interconnects, but I saw on the HyperTransport website a reference to a connector standard being developed. Certainly not USB style (that's InfiniBands area), it's more PCI-ish I guess.

I've read some docs, but I'm still not 100% sure if the memory aggregation happens at a hardware level in the crossbar or the memory controller. Either way, it seems to be transparent to software...

Having said that, I'd expect some tricks would make the platform go a little faster, but that's true of anything. My understanding of it is that the DIMMs are connected to the on-chip memory controller, but that memory can be shared via the HyperTransport links between processors. If that's correct, I'd expect to that for best performance code or compilers that can optimise memory allocation and an OS that can keep threads locked on a particular CPU. Or at least assign memory for the CPU a given thread is running on. HyperTransport is pretty quick anyway, so it probably won't matter too much, but I reckon that approach would give the optimium results.

Disclaimer - IANAEE


<i>Do I look like I care?</i>
June 17, 2002 11:00:34 PM

Quote:
<i>poorboy says:</i>
Certainly not USB style (that's InfiniBands area), it's more PCI-ish I guess.


Right, USB was just an example, I meant inter-motherboard, not intra-motherboard.
I can't see PCI being replaced anytime soon, though I would very much like to see 64-bit PCI slots on the dekstop. My TV tuner tends to use up the PCI bus fairly well.

<font color=blue>Hi mom!</font color=blue>
June 17, 2002 11:26:52 PM

Quote:
I agree, but I don't know much of it from a low level. I'd love to hear how programming for it will be, whether there will be optimizations that can be made for the way the platform works, or if it'll basically stay the same, or...

One thing I remember...due to the NUMA-like arrangement of processors and memory, Win32 would require a manufacturer-supplied driver for SMP to work. Win64-Hammer would likely already have such a driver, what with being designed for Hammer and all.

<pre>We now <b>return</b>(<font color=blue>-1</font color=blue>) to an irregular program scheduler.</pre><p>
June 18, 2002 12:00:03 AM

Quote:
One thing I remember...due to the NUMA-like arrangement of processors and memory, Win32 would require a manufacturer-supplied driver for SMP to work. Win64-Hammer would likely already have such a driver, what with being designed for Hammer and all.

Maybe not. From the Processor Presentation PDF:

Software view of memory is SMP
- Physical address space is flat and fully coherent...

I'm not too knowledgable about Win32 Programming specifically, but that looks driverless to me.

<i>Do I look like I care?</i>
June 18, 2002 1:41:42 AM

If sun use AMD opteron that a real tread to intel team.

Sun compiler sun OS sun server software AMD cpu Chipset ????.
Poor intel

cheap, cheap. Think cheap, and you'll always be cheap.AMD version of semi conducteur industrie
June 18, 2002 10:30:27 PM

Just to summarize (I know some of this has already been answered):

Quote:
Blank header: Above the CPU on the right, there are traces to what almost looks like an IDE header, just below the PCI slots. Maybe placement for a CNR slot?

This is absolutely hyper-transport. The traces from the CPU prove it. Hyper-transport is slated to be used as a PCI replacement, but I don't think that's why this particular one is there. This board has no AGP - the only "North-Bridge" function not directly included in the hammer line of procs. To communicate with the proc, AGP must be translated to HT. This is probably a test header for connecting additional devices (like AGP) to the HT bus. If you look closely, you'll notice that the other proc has one too.

Quote:
RAM banks: There's a crapload of them. Probably just testing for maximum stability with lots of DIMMs, but I wonder how many will find their way onto retail boards. Also, since there are two "channels", you'll need a minimum of two sticks. Do both CPUs need the same amount of RAM? It could cause some interesting scenarios if not, but nothing serious.

Yes, there are 8 slots per CPU. As this is an Opteron DP (clawhammer) and not an Opteron MP (sledgehammer) only one stick is required per CPU (two in total, min.) as the Opteron DP is single channel. When the Opteron MP boards sample (Q1 03?), there will need to be two sticks per proc - eight sticks for a 4-way system.

Technically, both CPUs don't need the same amount of ram, just as the CPUs don't have to technically run the same speed (just like the Athlon in dual proc setups). It will probably be up to AMD and the respective chipset and mobo manus to determine if they will allow disparate procs and memory amounts without BIOS errors/warnings.

Quote:
Power: There seems to be an awful lot of power regulation going on. Looks like the Hammer is a pretty complex platform, I wonder how that will effect both prices and smaller mobo makers producing motherboards for Hammer. We might see very expensive, but very good motherboards coming out.

As I said before, this is a very early mobo (probably one of the first Opteron DP boards (before the proc was even named Opteron - back when it was still just clawhammer). This configuration can be called pre-alpha. I'm certain that the power scenario will be refined prior to release in Q1 03 for the Opteron DP - especially after they have experience from the Athlon Ultra/64/Super/Magna/Titanium Ranger clawhammer that is due out Q4 02.

Quote:
This is just a test board, so it's not completely indicative of what retail (or even reference) boards will look like. It's also probably just the 800MHz samples of Hammer sitting on there.

They may not even be the 800MHz samples.

On the Sun side of the issue - Sun's use of Hammer has been rummored for some time already - originally thought mostly wishful thinking by most industry pundits. Recently I have been wondering what the big deal is with Sun scaling back on support/developement for Solaris 8/9 for Intel.

Now it seems almost obvious. Why would they keep developing a software platform for hardware platforms supplied by their greatest hw rivals (Intel, IBM, Dell). Why not just take that expertise and convert it to Solaris 9 for AMD! THis is very much like what IBM did when the started using PowerPC procs in their RS6000 range. If the hammer scales well, Sun may eventually shift up into its mid-range products. This would free up Sun's R&D resources to develop a better, faster, etc. (ad nauseum) Sparc proc for their high end. They could easily team up with AMD or another vendor to build "inexpensive" low to mid-range workstations and servers under the Sun brand while releasing Solaris 9 for the platform. They could even key the OS so that it will only run on their brand platform. And they always have Linux to fall back on (like IBM)....

If the thought I thought I thought had been the thought I thought, I wouldn't have thought so much.
June 18, 2002 10:40:19 PM

Thanks for the input, I completely missed the header above the left CPU. Do you have any links to more info about HyperTransport being used as a connectivity medium (e.g. replacing AGP)? I haven't really heard anything about it.

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!