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Processor speeds......

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July 4, 2002 1:22:26 PM

I am a little in the dark about the processors speeds, not about the speeds directly but how the speed that a certain chip can run at is decided.....

For example what is the actually physical difference between a Athlon 1Ghz and an Athlon 1.2Ghz?

Has it just been tested and found that it runs stable at a higher speed?

Do the long gaps between releases of different speeds of processor speeds have something to do with refining the manufacturering process?

More about : processor speeds

July 4, 2002 8:21:39 PM

Some processors are as we call: Down-Binned.
These are the result of downclocked processors on the same chip, just less clocked.
Normal processor speeds are using "Steppings", where the CPU maker adjusts the chip, and the surrounding packaging. Steppings ensure the complete stability of that chip, as well as optimum temperatures usually.

I hope I got it right!

--
:smile: Intel and AMD sitting under a tree, P-R-O-C-E-S-S-I-N-G! :smile:
July 4, 2002 8:50:02 PM

And downbinning is why Intel's P4 1.6A-2.0A have been able to overclock very well. Especially the 1.6A.

:smile: Falling down stairs saves time :smile:
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July 4, 2002 8:52:31 PM

Thx
July 4, 2002 8:56:13 PM

Well actually the idea of saying they OC very well is partially flawed. It's only a 2GHZ in reality and if a 2GHZ gets to 2.4GHZ with limitations, it explains why the 1.6A is called the OCer. But in reality it's a 2GHZ, not a 1.6A stepping that was original.
In anycase it OCs as hell, but the main highlight of that is its price.

--
:smile: Intel and AMD sitting under a tree, P-R-O-C-E-S-S-I-N-G! :smile:
July 4, 2002 9:01:16 PM

so if I could get a 1.6A i could overclock it to 2Ghz no problems?
July 4, 2002 9:58:31 PM

No it can get to 2.4GHZ almost guaranteed with the Retail HSF.
2GHZ is the real chip behind it, but Intel downclocked it to 1.6A and sold it that way, I guess it lowers stepping costs or something. It's like taking a GF3 and downclocking it to a Ti200 and sell it that way. It will easily "OC" to GF3 speeds because that's what it originally was! But that is not how they did the Ti200 btw, so don't get that in your head!

--
:smile: Intel and AMD sitting under a tree, P-R-O-C-E-S-S-I-N-G! :smile:
July 5, 2002 1:45:57 AM

Ummm, I'm afraid that's not entirely correct. There is no such thing as a fab process to make a 2.0 GHz chip. When Intel makes the chips, they aren't rated at a specific frequency. So a chip that will eventually be marked as 1.6 GHz is made the exact same way in the exact same machine as a chip that will eventually be marked 2.8 GHz. The only difference is, as said above, stepping. The OLDER, the chip is, the lower stepping it has (steppings are minor improvements made in the design). So a brand new chip that came out of Intel fab plants marked as 1.6 GHz will have the exact same hardware as a 2.8 GHz chip that came out at the same time the 1.6 did.
Intel makes Pentium 4 chips, period, they're not made for any type of frequency. The stress tests Intel put them through later will determine the "maximum" frequency. So if 100 Northwood chips were made, 90 of them may pass the test at 2.4 GHz, while 10 of them only passed the test at 2.2 GHz. That's not what they're marked at however, marketing determines that they only need 10 2.4 GHz chips, 20 2.2 GHz chips, 30 2.0 GHz chips and 40 1.8 GHz chips. So even though 90 of the chips made pass the 2.4 GHz test and would run stable at 2.4 GHz, only 10 of them are marked and sold as 2.4 GHz chips while 80 other chips that work perfectly fine at 2.4 GHz are marked and sold as lower-speed chips. That's the gamble when you're overclocking, whether you got one of those 10 chips that only make it to 2.2 GHz or whether you got a 2.4 GHz chip that was marked at a lower speed. That's when yields come in. With an Athlon, only 20 out of 100 chips may make it to 1.73 GHz, so overclocking with that particular core isn't a good bet since you only have a 20% chance of getting a good chip. With the Northwood example above, you have a 90% chance of getting a chip that makes it to 2.4 GHz. Of course, these numbers are made up, but it demonstrates the point.
July 5, 2002 2:07:18 AM

Hmmmm... thanks for the great insight. I never knew that. So are you saying that AMD's yeilds aren't as good as Intel's? I've actually heard the opposite?

:smile: Falling down stairs saves time :smile:
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July 5, 2002 5:21:26 AM

The 1.6A and 1.8A both do 2.4GHz fairly easily, but overclocking the 1.8A is easier because the bus speed would be 133 (QDR533) instead of 150 (QDR600).

<font color=blue>At least half of all problems are caused by an insufficient power supply!</font color=blue>
July 5, 2002 5:32:26 AM

Not AMD in general. The Athlon's yields aren't as good as the Northwoods. This is primarily due to the fact that the Athlon's K7 core is at the top of its architectural scalability while the Northwood (P7 core) has just begun. It's suppose to scale to 10 GHz and possibly even beyond. Obviously it'll be easier to attain better yields with a core designed to have great yields at the low-ranged GHz scale.
July 5, 2002 12:42:40 PM

Quote:
suppose to scale to 10 GHz and possibly even beyond.

10GHZ+???!!!! :eek:  :cool: .... Cool..

:smile: Falling down stairs saves time :smile:
July 5, 2002 1:52:50 PM

Yeah but with the Prescott's improvements, I have my doubts on that claim without adding SOI, extra pipeline stages or whatever. The K7 did not go 10 times its first speeds, so I don't see how the P7 would. I KNOW they have 20 stage pipelines, but that is how it has always been with new cores (excluding K8), they almost double the pipeline or nearly.
So whether or not it can do 10GHZ, I have my doubts.

--
:smile: Intel and AMD sitting under a tree, P-R-O-C-E-S-S-I-N-G! :smile:
July 6, 2002 12:30:41 AM

I thought they were originally projecting for 5 Ghz by 04-05. I could be wrong, but it seems like the P7 line has plenty of life left, easily a few more Ghz. Unfortunately for AMD I doubt even with the K8 they will hit 3Ghz...maybe, but the way things scaled for the Athlon, unless they hit .09um process, it just seems unlikely to see anything beyond 2.5Ghz or so on their .13um process.

"When there's a will, there's a way."
July 6, 2002 6:34:15 AM

Pipelined processors (since the 286's I think and probably even before that) all have a basic 5-stages. Fetch, decode, schedule, execute, release. Since then to the P6 core (Pentium Pro - Pentium 3), the method of hyperpipelining to a 10-stage integer pipeline increased the maximum scalability to 1.6ish GHz (with the Tualatin core) and probably has even more room to go with further optimizations (look at the t-bred, it can reach 2.0 Ghz and a little beyond in some cases). The P7 core's jump to a 20-stage integer pipeline (and an even longer FP pipeline) was a huge jump. Either way, projections of the core was to 10 GHz and probably beyond.
July 6, 2002 10:20:50 AM

Someone mentioned the 0.09 process, check out the amd website, you will find a road map that says they will be using 0.09 SOI in 2h03. This is the only bit of the AMD roadmap that excites me. The intel road map does not reveal much about next year, but I somehow doubt intel will move to 0.09 next year, because notrhwood has life left in it. But on the opposite way intel will not want to get behind AMD in R&D.

The roadmap shows however they will be making the following processors together:
Barton
Clawhammer (this will be first to move to 0.09)
Sledgehammer
July 6, 2002 1:36:10 PM

Prescott will be made on the .09 micron process. That is one of its touted features and has been stated officially I think. Prescott is currently scheduled for 2Q 2003 and may be moved even sooner if Hammer really does well, so that should give you some indication of when Intel would move to the .09 micron process.
July 6, 2002 3:38:12 PM

cool, so we gonna have a 0.09 war on our hands!

BTW what process was the Athlon thunderbird built in and what athlon core was before the T-Bird, what process did that use?
July 6, 2002 4:39:38 PM

The very first pipelined x86 CPU was actually the 80486. This was so the 486 could achieve 1 instruction per clock cycle and keep up with the RISC CPUs that were allready pipelined.

Not trying to spread FUD, but as far as I know, the Pentium 4 (Willamette definate and possibly NW) only has one instruction decoder, this means that, as far as I know, it can only to 1 instruction per clock cycle, hence the need for higher clock speed. The PIII and the Athlon can do upto 3 instructions per clock cycle as long as it's optimised for it, although out of order execution helps make this less nessesary. In fact, the reason why the Athlon's FPU performance is so great is that it has 3 FPU pipelines.
July 6, 2002 5:08:27 PM

The origional Athlon was .25micron, then they moved to .18micron and now with tbred they are at a .13 process.

I think an important thing to read into this thread is that by no means do Mhz mean everything with a CPU. The Mhz is simply how fast the clock cycle on the chip is. It is entirely possible for a 100mhz chip to beat a 2000mhz chip. If the 100mhz chip can do 20 ops per cycle, and the 2000mhz can only do .5, then the 100mhz chip would obviously be the best bet.

I for one would like to see an industry standard built to replace the Mhz/IPC chatter thats going on. Then instead of having a Mhz war, we could have a true measure of a CPU's performance. Intel seems to not want this, thus, they continually push off any offers of such. The P4 was purely built from a Marketing perspective, pumping Mhz in peoples face along with wierd aliens and blue men builds the Pentium Brand.
July 6, 2002 7:00:52 PM

That's not entirely fair. I'm not an Intel lacky or anything, but they did have something beyond simple marketing in mind with the P4 architecture. I'm sure the marketing slugs that appear to run Intel got all over the design concept, and just drooled all over the marketing possibilities of high clock speeds. However, the original concept arose from the legit idea that it was FSB / memory bandwidth that were holding back higher processor performance moving forward. Hence the deal with Rambus, which was a big mistake for Intel in retrospect
July 6, 2002 7:43:21 PM

Intel had the power to support DDR over RDRAM a long time ago, but they couldn't due to their ties with Rambus. Had Intel supported DDR RAM when the P4 was first released, we'd probably have Dual-channel DDRII by now.

:wink: <b><i>"A penny saved is a penny earned!"</i></b> :wink:
July 6, 2002 8:01:22 PM

RDRAM and their prices/royalties....killed themselves. Having Rambus pouring $$ into developing newer, better Ram technologies isnt a bad thing. Too bad they had that price premium upon P4 launch....If it took off, we couldve had a developer trying to catch up w/ proc technology.

I sold my sig for $50.
July 6, 2002 8:56:51 PM

Rambus RAM is currently not winning for these two main purposes:
1) Lack of innovation, we have had PC800 for over 3 years, PC1066 has yet to be mainstream, so Rambus is dragging ass.
2) Price-wise not many would afford a P4 RDRAM system back in the first days. The PC1066 is based on 133MHZ or the same as PC2100 DDR, which means both work well for synchronous operation on the P4's new bus, so why is the PC1066 so costly then? If it was put as single channel, at 2.1GB, it nearly costs twice the PC2100 DDR for the same performance and possibly worse latency.

--
:smile: Intel and AMD sitting under a tree, P-R-O-C-E-S-S-I-N-G! :smile:
July 6, 2002 11:38:26 PM

Exactly, Intel made a big mistake in retropect in signing an agreement with Rambus that require them to pay a big penalty for going with DDR before the start of this year.

However, to give RDRAM some credit, it does appear to facilitate dual memory channel configuration (due to the serial architecture, as compared to the parallel SDRAM).
July 7, 2002 5:08:17 PM

Posted by Uriki:

>>>I for one would like to see an industry standard built to replace the Mhz/IPC chatter thats going on. Then instead of having a Mhz war, we could have a true measure of a CPU's performance. Intel seems to not want this, thus, they continually push off any offers of such.

Such a standard does exist - <A HREF="http://www.spec.org" target="_new">http://www.spec.org&lt;/A>. Note that Intel is a member, so you may need to rethink your position.

And as for marketing, well, they're always going to play up whatever sells. That's what they get paid to do.
July 8, 2002 4:23:27 AM

Quote:
The very first pipelined x86 CPU was actually the 80486. This was so the 486 could achieve 1 instruction per clock cycle and keep up with the RISC CPUs that were allready pipelined.

I may not be familiar with the exact history of MPU's but didn't the 8086 have an "extended architecture" in which it split its operations between execution and release?

Quote:
Not trying to spread FUD, but as far as I know, the Pentium 4 (Willamette definate and possibly NW) only has one instruction decoder, this means that, as far as I know, it can only to 1 instruction per clock cycle, hence the need for higher clock speed. The PIII and the Athlon can do upto 3 instructions per clock cycle as long as it's optimised for it, although out of order execution helps make this less nessesary. In fact, the reason why the Athlon's FPU performance is so great is that it has 3 FPU pipelines.

Actually, I don't think that's true. The P4 has a decoding unit that can decode 3 x86 instructions into micro-ops to store in the trace cache (it either uses the decoding unit or the micro-code rom depending on how complex the x86 instruction is). The problem arrises when micro-ops are fetched from the trace cache. The P4 has a limitation of fetching 3 micro-ops from the trace cache. This is all good if all 3 x86 instructions were simple x86 instructions that are each decoded into 1 micro-op (and most x86 instructions are) however, when you get complex x86 instructions that could decode into 2-4 micro-ops, you have a bottleneck. It can decode enough x86 instructions into micro-ops but it can't fetch enough micro-ops. The Athlon, on the other hand, can decode 3 x86 instructions per clock and fetch up to 6 micro-ops per clock (if the 3 x86 instructions decoded into more than 3 micro-ops). That at least is the limitation with the decoding part.

And the Athlon's strong FPU performance, despite common myth, is not due to its 3 FPU units. The P3 had 2 FPU units and it provided similar FPU power per clock to the Athlon. The reason the P4's 2 FPU units aren't as powerful is because of the limited FXCH move instruction support. This operation is commonly used in modern FP intensive code and the P4 can only fetch 1 FXCH instruction per clock.

Now while the decoding limitation of the P4 does account for some of its less work per clock, decoding and fetching is only a bottleneck some of the time. Data dependencies would prevent any MPU from achieving the whole 3 x86 instructions per clock that it strives for. On average, I would say the Athlon achieves around 1.5 with most of modern code and the P4 around 1.25. The P4 actually deals with data dependencies better than its predecessor, the P3 or the K7 design, however, there's still the lack of FP power and lack of fetch abilities that really tie it down. The 20-stage integer pipeline also increases the hazard of data dependencies and while the P4 does have some very good methods of dealing with it, it still isn't enough to surpass its predecessor or the K7 as far as branch code.
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