New T-breds

cool.

too bad that athlon`s FSB is a DDR structure. it`ll be better if they used intel`s quad-bus. with the same clock, twice better performance.

my hammer will make things better.

"Is Celeron good?"
"No. Celeron is bad."
LOL

rambus, pc800(dual) = 3200mb/s
rambus, pc800(single) = 1600mb/s <--sucks, DDR is better

DDR pc1600 = 1600mb/s
DDR pc2100 = 2133mb/s
DDR pc2700 = 2700mb/s

but the AMD`s FSB`s wandwidth is (if FSB=133MHz) 2133mb/s so a faster ram wouldn`t really help(the nforce`s dual channel DDR didn`t really kick up performance)

amd needs to make chips with faster FSB, or use that quad-bus stuff used in p4, then rambus would really be effective.

by the way, u knwo about VIA`s apollopro266? it`s a p3 chipset, using DDR. p3`s FSB133 is 1066mb/s fast, while the DDR266 is twice as fast. the DDR didn`t have any benifits over the SDR pc133. so u see, the front side bus needs to be as fast as, or faster than the RAM speed.

"Is Celeron good?"
"No. Celeron is bad."
LOL

Yeah, but at the same speed, say 1666Mhz, an Athlon with a 166Mhz FSB will have a nominal performance gain over an Athlon with a 133Mhz FSB. This effect is even more pronounced on the Pentium4, it practically THRIVES on cache and memory bandwidth.

"When there's a will, there's a way."

The needed memory bandwidth and cache latency is almost directly (in fact, probably exponentially) related to clockspeed. Processors attempt to fetch and decode a certain amount of instructions per clock. To do this, you have to spend a lot of time looking at the data in the cache, in memory, prefetch (in the case of the P4 and Palomino), and of course, still have enough bandwidth left asside to keep the processor fed with incomming instructions every clock. The more clockcycles per second you have, the more instructions the processor will have to "sift through" in order to find instructions in which it can process independently. This is why huge amounts of bandwidth are needed.
The P4's higher clockrate means it will indeed need faster memory and lower latency cache in order to keep the processor fed. At 1.8 GHz, the current K7 line doesn't attempt to fetch that many instructions per second (although it does finish a bigger percentage of the ones it fetches per second than the current P4 design).
At 2.53 GHz, the availability of instructions is absolutely crucial to keeping the P4 pipelines filled. And as another post demonstrated, a hyperpipelined design will only be able to maintain relative IPC if the pipeline is filled at all times with useful instructions.

yeah, i read this in another newspaper in korea. seems not a rumor, though i think that the reporters over here translated the site u have linked up there.

"Is Celeron good?"
"No. Celeron is bad."
LOL