Don't efficient caching algorithms should be capable of eliminating those latencies? The fact that the Via KT266a with PC2100 is outperformed by the KT333 with PC2700 DDR-RAM quite proofs this. Though the performance increase there could also be due to general optimisations.
One thought, though. Shouldn't the increased data-throughput from the RAM to the northbridge be capable of compensating the latency induced by the async clocks? I mean, if just look at the numbers, and compare PC2100 CL2 DDR-RAM to PC2700 CL2 DDR-RAM, the amount of clock cycles you need for the RAM to respond is the same, but at 166 MHz 2 clock cycles is shorter than in 133 MHz operation.
Wait, let's calculate something (plz, proof me if I'm wrong ... or if I'm calculating foolish things ...). 133 MHz implies a 7.5 nanosecond clock cycle, 166 MHz 6.0 ns. 2 clock cycles equal 15 ns and 12 ns, respectively. So, PC2700-CL2 RAM provides data 3 ns faster. This happens to be half a clock cycle of the FSB bus (at 133 MHz), which can be taken advantage of in a DDR-system, because there, two times per clock cycle, data is transferred. So I think a a PC2700 system is able to provide data with LESS latency than a PC2100 system.
In a constant data stream, I guess, the asynchronuous bus clocks could lead to problems, since the RAM is providing data at about 1.25 times the FSB's speed. So about once every four clock cycles the RAM is one clock cycle ahead of the FSB. But I think this problem is eliminated quite easily by implementing caches on the northbridge.
So, actually, I don't see any lantency-enlarging mechanisms in this setup. But since I have read all over the internet that asynchronuous setups actually DO enlarge the latency, I must have made a mistake here ... Hmmm ... Confusing ...
Greetz,
Bikeman
<i>Then again, that's just my opinion</i>