new very intresting hammer document

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Some intresting (I think) points I compiled:

1.Hammer has 3 cycles latncy for 32bit add compared to 4 on Athlon.

2.Hammer 64bit add has 4 cycle latncy.

3. AMD shows tow types of 8gen Athlon:

one for single processor system with 1 16bit
HyperTransport bus.

one for dual processing with 2 8bit HyperTransport

I think they mean its the same processor that -
with diffremnt HyperTransport "modes" for single
and dual processoring.

4. AMD shows two Diffrent parts for opteron
procesores :

Workstation part for 2p systems:
2 16-bit HTT Links
512/1024KB ECC protected L2

Server part for 8p systems:
3 16-bit HyperTransport Links
1M/2MB ECC protected L2

Both come in 940pin mPGA
Both support up to 8Gb of local (per node) memory.

5. L2 Cache:
256K-Byte/512K-Byte/1M-Byte ECC protected L2 cache
16-way associative
Improved L2 -> L1 bandwidth (>2X Athlon)
L2 backs up branch prediction and pre-decode
information and data.

6. What's that? :

Full Pre-decode and Branch Identification in L2
Cache New and unique to Eighth Generation Family
of Processors
Reuses L2 ECC bits on clean/shared instruction
lines and on extra bit

7. Data movement over the HyperTransport™ bus does
not use any CPU machine cycles.

8. Some latncy figures given for multi-processing

Idle Latencies to First Data
1P System: <80ns
0-Hop in DP System: <80ns
0-Hop in 4P System: ~100ns
1-Hop in MP System: <115ns
2-Hop in MP System: <150ns
3-Hop in MP System: <190ns
(Assume a processor clock of 2.4MHz)

Average unloaded latency in 4P system (page miss)
is designed to be 140ns.

Average unloaded latency in 8P system (page miss)
is designed to be 160ns

These seem to compare nicely to EV7 given numbers.

9. Integrated DDR Memory System Controller:

"<1/2 latency of current Stare of Art (AMD Athlon
XP processor)" (given which chip-set?)

>4X the bandwidth of current State of Art (AMD
Athlon XP system)

10. AMD shows a "Asymmetric 2P low cost desktop
system" with one Opteron processor (dual DDR)
described as "Foreground processor" connected to
one 8gen Athlon processor described as
"background Processor". the opteron handles I/O
(page 47).

11. page 49. "AMD8131™ in String of Pearl
Configurations" with one opteron processor and
multiply (up to 31) AMD8131 PCIX tunnels.

12. page 50. "AMD Opteron™ 1U/1P Server" one opteron
connected to two PCIx tunnels (16bit HT for each)
each with "SSL Security Macro Processor". also
connected to the regular I/O HUB.

13. page 51. "1U/2P AMD Opteron™ Server" nothing
special here sorry ;)

14. page 52. "1U/2P AMD Opteron™ Server" each opteron
connected to "SSL Security Macro Processor". one
opteron is connected to PCIx tunnel. the other
to "Programmable Logic Device" apperntly for scsi
and Gbit ethernets. the same connection also has
the I/O hub.

15. page 53. "StarFabric™ Storage Server". two
one connected to I/O hub from one HT the other HT
is connected to: "StarFaberic
(622Mb)", "StarFaberic
Switch", "StarFaberic To PCI Bridge".
the other processor is connected to "Broadcomm
BCM1250" from one HT, "IPsec Security Macro
Processor" from the other HT.

16. page 54. "Storage Server FiberChannel"
two opterons.
1. one HT to I/O Hub. one HT to "FiberChannel
2. one HT to Broadcomm BCM1250 and PCIx tunnel.
one HT to "IPsec Security Macro Processor".

17. page 55. "Quad AMD Opteron™ TCP/IP Offload Engine"
one of the opteron is connected to a "SSL
Encryption TCP/IP off load engine" and a "Modular
Array ASIC"

18. "Non-Traditional Topologies 28G FLOPS
Recognition Engine". Well people this one you'll
have to see for you'r self - it has _3_ opterons
with one of them connected to _4_ 8gen Athlons...

19. page 57. "AMD Opteron™ Cubed – 8P Server Topology"
Only three nodes are 3 hops away
No nodes are 4 hops away.

20. new design for balde servers:
"AMD is participating in major OEM Blade efforts
Establishing an “Open Standard” based on cPCI
and HyperTransport

Many “Value” issues
Power - AMD will offer lower power Hammer
Density - 64-bit computing in Blades
System Management and Fail-Over
Network Management (Interconnects as well as
Scale-Out & hot-Swap

Next Generation Applications
Storage Area Networks (SAN)
High Performance Computing (HPC)
Mobile Telephone Switch Office (MTSO)
On Demand Content Delivery (ODCD)
Recognition engine

Possible future chipset directions to optimize
Integrated OC-48
Integrated TCP Offload Engines (TOE)
Integrated dual processor"


Well it seems that AND is guning very strongly for opteron on the server/workstation markets. along with an effort to integrate many devices for specific tasks by utilising Hammers HyperTransport links. the Hammer system design seems very flexible by utilizing HyperTransport for a vrity of tasks.

This post is best viewed with common sense enabled<P ID="edit"><FONT SIZE=-1><EM>Edited by IIB on 08/22/02 10:05 PM.</EM></FONT></P>
3 answers Last reply
More about intresting hammer document
  1. Please fix your link.

    <b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>
  2. fixed

    This post is best viewed with common sense enabled
  3. Too funny... I just posted that power point slide show.

    It is good stuff...

    <b>"If I melt dry ice in a bathtub, can I take a bath without getting wet?" - Steven Wright</b>
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