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Is Front Side Bus running at 533mhz???

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August 22, 2002 11:02:53 PM

Two quick questions, I upgraded to a P4 2.26 ghz with an Asus P4S533 mother board and 512 pc2700 ram. I used the Asus probe utility and found 2 things that seem wrong. One is the system clock is running 133mhz rather than 533. The chip speed is set to 2.26 ghz, but I'm assuming that means the FSB is only at 133. I checked the settings in setup and there are no selections for 533.
Also, when I run the utility it says the cpu fan is not running as fast as it should be (2200) it's only around 1650. . .any idea how to change that.
Thanks in advance
August 22, 2002 11:24:51 PM

Ok...

its kinda like a 305 and 350....ones a 5.0 Liter and the other is a 5.7 Liter.....the 350 will always be better though.....LoL for real though.....

the CPU runs at a FSB of 133MHz.....that FSB is quad pumped though.......which effectively makes it 533MHz...just like an Athlon...teh bus is double pumped though in its case.....so 133 translates into 266.....just liek 133 for a P4 translates into 533......therefore nothings wrong....

as far as ur fan goes........theres a few different ones for the P4.....some run at 2200rpm and others at around 1600 like urs......nothings wrong..its fine =)

<A HREF="http://www.anandtech.com/mysystemrig.html?id=13597" target="_new">-MeTaL RoCkEr</A>
August 23, 2002 1:42:27 AM

one day without the occasional *BUMP* to that 'search before you post' and you get these questions again.. no disrespect intended

<font color=green> there's more to life than increasing its speed -Ghandi</font color=green>
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August 23, 2002 2:28:20 AM

Intel is not using a 533MHZ FSB. Crash is right, this is market drivel. It is running at 133MHZ, just like P3. Only difference is it uses 4 times the data at the same clock. So it's a 256-bit 133MHZ data bus, in a way.
I have no idea how they did it, if DDR itself is not the most easy thing to do, and I have yet to find any docs that explain how the Quad Pumping works.

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August 23, 2002 3:02:12 AM

the quad pump works like this: imagine two free running clocks, they're really strobes that's why the clocking scheme is called "source-synchronous" - when the driving chip sends the clock (strobe) to the receiving chip instead of relying on a common system clock.. anyways, there's two of them, strobeP and strobeN, 180 degrees out of phase from each other so that when one strobe is rising the other is falling. in 1 clock period, each strobe can fall, then rise... let me say that differently,

for each period, strobeP falls then rises while strobeN rises and falls. you see, there's two falling edges on each period that can latch in data waiting at the flip-flop's input (the basics of GTL+ signaling)

intel fsb data is really running at 133MHz, but in 1 period, you have a high and low (1 for half period then 0 for other half for example..it could be 01,11,00 as well) so you pretty much have 2 data samples for each hertz, hence 133*2=266MT/s.. combine that with the two strobes each going negative once during that same period (you can also think of it as the crossing point of the two strobes) you get to multiply it by two again, hence 266*2=533MT/s.


<font color=green> there's more to life than increasing its speed -Ghandi</font color=green>
August 23, 2002 3:12:06 AM

that is why people should refer to the fsb as having 533MT/s (mega transfers per second) instead of 533MHz (mega hertz per second).. it's really transfers that matter.

the reason people still use 533MHz is because that's what it feels like if it wasn't GTL+ signaling, like CMOS or TTL where the rising or falling edge of the main system clock latches in data at the FF's input. it feels like data is going at 533MHz with a clock at 533MHz that latches data on one edge... latching in data as alot of people are aware of requires meeting certain setup/hold time (you have to have clock fall/rise in the middle of the data sample, ow you'd miss the data sample because you're either clocking too early, which means violating setup time, or clocking too late, which means violating hold time....

with source-synchronous clocking you send data then your strobe (clk) exactly in the middle in order to meet those timing requirements. if both gets to the receiver like how they came out of the driver, it's honkie dorrie, but if anything happens along the way, then your data is screwed.

<font color=green> there's more to life than increasing its speed -Ghandi</font color=green>
August 23, 2002 3:14:09 AM

this is all from web search (my fav hobby) and reading all i can about EE. i'm still in high school so don't blame me if my info isn't elegant or correct for that matter.

<font color=green> there's more to life than increasing its speed -Ghandi</font color=green>
August 23, 2002 3:23:40 AM

my first time attempting a quad-post.

if you get your hands on ddr or agp4x/8x clocking you'd see the same source synchronous clocking scheme as well.. wonder why.. oh yes, intel has it hands on all of them.


<font color=green> there's more to life than increasing its speed -Ghandi</font color=green>
August 23, 2002 1:13:50 PM

Not here, but Crashman made that point in another thread.


<font color=red>A platform is not an oil rig.</font color=red>
August 23, 2002 2:08:59 PM

The easiest way to visualize it (though it is a grossly simplified way to look at it that lacks the true complexity and details that make it so difficult to work with physically) is to think of it as a sine wave.

  |<font color=red>/\  </font color=red>|<font color=orange>/\  </font color=orange>|<font color=yellow>/\</font color=yellow>
  |<font color=red>  \/</font color=red>|<font color=orange>  \/</font color=orange>|<font color=yellow>  \/</font color=yellow>

Now the P3, the AXP, and the P4 all have a wave of the same frequency. (In other words, the number of times the wave peaks during the same perdiod of time is the same.)

However, the P3 only sends data when the wave peaks.
The AXP sends data when the wave peaks <i>and</i> when the wave bottoms out.
The P4 sends the data when the wave peaks, bottoms out, and during the two middle points.

It all happens on the same 133MHz wave. The difference is how effectively that wave gets used. (How many transfers occur in a single wave.)

<pre><A HREF="http://www.nuklearpower.com/comic/186.htm" target="_new"><font color=red>It's all relative...</font color=red></A></pre><p>
August 23, 2002 4:04:46 PM

Thanks for the info, it was very helpful, I'll search first next time.
Cheers
Camaro
August 23, 2002 5:46:59 PM

Quote:
However, the P3 only sends data when the wave peaks.
The AXP sends data when the wave peaks and when the wave bottoms out.
The P4 sends the data when the wave peaks, bottoms out, and during the two middle points.

huh? that might be the right way of saying it, but maybe too basic.

i'd rather you simplify it to square pulses because that's more realistic than sine wave..

anywayz, visually 1 clock period doing this:
.__
|...|
|...|___

it's complement clock is doing this in the same period:
....__
...|...|
__|...|

GTL+ signal clocks (latches) data in a flip-flop on the negative going edge so if you have two negative going edges in 1 clock period (1/frequency), than you can essentially clock in data twice in 1 period.

now imagine a 133MHz square pulse running like this:

....___.....___....
.0.|.1.|.0.|.1.|...
__|....|__|....|___

so in 1 period, you can have two bits (data samples).. essentially having 266MT/s.

refer to my previous explaination for the guts.


<font color=green> there's more to life than increasing its speed -Ghandi</font color=green>
August 23, 2002 6:43:20 PM

Very nice info, except even with your previous post, the use of these complex words, will never reach to me!
Maybe Ars Technica has an article explaining it, they usually use their own pics to help visual people like me. They often also create them in GIF animations. So thanks again, but I can only grasp it if I had the visual aspect that few websites like Ars can do.

TO Slvr, what do you mean by the 2 middlepoints?

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