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clawhammer

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August 30, 2002 10:08:29 AM

has any body got anyinformation about the amd clawhammer with a 800 mhz fsb and realese dates and prices

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August 30, 2002 10:56:38 PM

Even though the northbridge is integrated it still has an FSB, however I think unless the memory technology comes along soon an 800Mhz FSB is miles off, maybe the claw hammer will use rambus?

Anyway yes clawhammer for desktop should be out end of the year.

I will not be suprised if the 64bit chips from AMD and intel only run at 1Ghz or so, if intel with the itanium is anything to go by they have just released a 1.2Ghz itanium.

Here I am assuming that the Prescottt will run IA-64.
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August 31, 2002 12:33:41 AM

Quote:
I will not be suprised if the 64bit chips from AMD and intel only run at 1Ghz or so, if intel with the itanium is anything to go by they have just released a 1.2Ghz itanium

You're contradicting yourself when you say intel will probably release a 1ghz 64bit processor, and then say they already have a 1.2ghz 64bit processor.

Prescott is not a 64bit processor.

This sig runs too hot.
August 31, 2002 12:41:25 AM

hey orangewolf, i thought u didnt like amd?

--------------------------------------------------
My computer is so fast it proves the theory of relativity wrong... :eek: 
August 31, 2002 2:14:14 AM

Yeah, troll...

BTW what you're stating is a Prescott, not a CH. CH won't have an FSB directly, from what AMD states.

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
August 31, 2002 3:43:05 AM

Nah, Prescott probably won't have IA-64 support. If it does, then it will be a BIG surpise to alot of people. Tejas, the successor to Prescott, is rumoured to have IA-64 extensions.

Also, as Eden said, because of Hypertransport, Clawhammer won't have a <i>real</i> FSB, and it's basically unknown at what speed the "FSB" will run at. The only thing I heard about it is that Hypertransport can clock as high as 800mhz per channel/link.

Clawhammer, based on my estimates, should be out in limited supply in december, and there should be a plentiful supply in january, or february 2003.

- - -
All good things must come to an end … so they can be replaced by better things!
August 31, 2002 4:41:37 AM

That 800 MHtz is the demo core clock speed. For some reason, they haven't bumped that up yet.

Knowledge is the key to understanding
August 31, 2002 10:56:39 AM

I think this is where the 800mhz fsb rumor came from-

http://www.theinquirer.net/?article=5134

but like the article says 'It is probably just "roadmap shorthand" for the speed the Hypertransport bus runs at, we think.'
August 31, 2002 4:44:52 PM

Sorry my post was confusing but i meant to say, i would not be suprised if the Clawhammer previewed at 1Ghz.

I assumed abeit stupidly that the prescott was going to run IA-64. Are you seriously telling me the prescott is only a 32bit processor?

BTW what I was saying about the FSB for clawhammer was that memory generally runs at FSB speed and as DDR is not up to that speed yet I assume AMD are going for a 200Mhz FSB (DDR 400). Either that or amd have some well hidden trick up their sleeve..QDR???

But anyway this is all speculation so I will wait and see, but could someone clear up the prescott thing?
August 31, 2002 5:14:19 PM

Hey, if it doesn't have a FSB, then how are we gonna overclock it? Anyone thought of that, or is it gonna be factory locked?

<i>Past mistakes may make you look stupid, but avoiding future ones will make you look smart!</i>
August 31, 2002 10:56:39 PM

Nobody so far knows man, it's one of the biggest mysteries aside the FSB of Hammer.

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
August 31, 2002 10:58:32 PM

According to a link by bum_jcRules, Hammer's bandwidth should actually be up to 19.2GB/sec!
I am not sure how and what it means, but that would mean that we need DDR II to really push the potential.
Anyway this may all be false, just check the RAM forum and search for his post about Hammer's bandwidth.

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
September 1, 2002 1:25:38 AM

Clawhammer will have an 800MHz Hypertransport link. It has a completely different, dedicated channel to its memory. This is unlike any desktop level CPU that's ever come before to my knowledge. Initially, Clawhammer will support 166MHz DDR SDRAM to be used with the Clawhammer.
And yes, Prescott will be a 32-bit processor. The question is, so what?

"We are Microsoft, resistance is futile." - Bill Gates, 2015.
September 1, 2002 3:57:44 AM

Are you saying that's the hypertransport bandwith PER channel? That's got to be false for sure.

imgod2u, ahh, so the rumours really are true. CH will have an 800mhz. HT link. Boy, that could really solve all the bandwith problems the K7 core is having, if combined with the on-die mem controller. Seems that Prescott having an 800mhz FSB no longer sounds far-fetched, does it. It seems that Prescott will start with 667mhz, then go up to 800mhz. Tejas is rumoured to be "up there" at about 1200mhz FSB. That would need some SERIOUS bandwith.

- - -
All good things must come to an end … so they can be replaced by better things!
September 1, 2002 5:55:14 AM

Keep in mind that Hypertransport is an 16-bit link in the case of the Clawhammer I think bidirectional. Which means at 800MHz, it'll effectively provide 1.6GB/sec both ways. Hardly something to compare to the 6.4 GB/sec 800MHz 64-bit FSB Prescott will have. Although keep in mind this link is dedicated to the chipset while memory has its own 64-bit DDR channel.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.
September 1, 2002 3:32:58 PM

That is what I was wondering, if HyperTransport doesn't match System bus bandwidth, then why is it so touted? Is it gonna boost PCI, AGP ports or what?

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
September 1, 2002 5:58:03 PM

Hypertransport is the bandwidth for the CPU to various interfaces. It is special because it links the northbridge (on die) to the southbridge (off die), it is actually the fastest link between North and south bridge chips I believe. That is why it is special. Yes hypertransport does work at 800Mhz i think because it is one of the most important links on the motherboard.

Because the FSB does not link north and south bridge chips usually, infact in some cases the PCI bus was used to link north and south bridge chips in the past.
September 1, 2002 6:48:24 PM

The reason Hypertransport is touted is not due to its supremely high bandwidth (which it doesn't have currently) but rather its elegant implementations in multiprocessing environments. It is a point to point protocol which means instead of all the CPU's in a multiprocessor setup sharing a link to a central chipset and memory controller, each will have its own dedicated HT link and an HT link to the other CPU's. This is much more effective than the traditional shared bus in some things while it does have some bad aspects.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.
September 1, 2002 10:42:43 PM

Is hypertransport an evolution of the Alpha bus AMD have used in the Athlon MP?

eg. Each processor has it's own bus.
September 1, 2002 11:13:11 PM

Sorta. It does share the point to point concept that the Alpha EV6 bus had. Although the EV6 bus isn't as versatile, nor was it serial. The biggest improvement would be that it uses very few traces and therefore, would be much easier to manufacturer, not to mention have a greater distance and be more flexible as far as design.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.
September 2, 2002 1:00:10 AM

What are the bad aspects of the HT? In other words, what are the disadvantage?

Also, in a normal user's comp operation, what would HT offer that can be noticeable? I heard that it would in fact speed up game level loading because the data is flown faster.

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
September 2, 2002 5:29:35 AM

The disadvantage of course, with any point to point technology, is the increased pin count you'd need in order to maintain a dedicated link to each of the other components. Notice how many pins are on the Hammers. This takes a lot to manufacturer and test and a lot to maintain.
A second side-effect is that since there is no "centralized" nature. It's difficult to coordinate data and calculations. So the CPU's would have to spend time checking not only its memory pocket but the other CPU's memory pocket and since there is no centralized place where all the CPU's get their stuff from, it's harder to coordinate efficient multiprocessing. Of course, I expect Hammer and many other point to point interconnect based CPU's in the future to have some methods to deal with these issues.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.
September 2, 2002 6:43:33 AM

Just to tell you that this is one of the best threads I've read for some time. No futile discussions, just information and really interesting. Great!


DIY: read, buy, test, learn, reward yourself!
September 2, 2002 6:46:26 AM

Clawhammer has more than 1.6 GB/sec memory. The clawhammers memory controller is seperate from the hypertransport link. Hypertransport is used for the CPU to communicate with the other parts of the computer (PCI, AGP, IDE, etc.). The clawhammer will incorporate an on-die 128-bit DDR333 memory controller for 5.4 GB/sec bandwith. The sledgehammer (Opteron) will incorporate a dual channel DDR333 controller for 10.8 GB/sec bandwith. However, these chips also have the ability to have their on-die controllers "turned off" so other chipsets can be made that can incorporate newer, faster memory technologies (DDR400, DDR-II, etc.) Also, the hammer chipsets don't just have 1 hypertransport links, they have 3 or 4, which allow I think 6.4 GB/sec badnwith total in hypertransport links in single-CPU systems.

"Trying is the first step towards failure."
September 2, 2002 12:09:47 PM

The increased pin count, hence the clawhammer has a gap in the center like cpu's today where the die is and the sledgehammer does not, lots more pins!

Yeah I just read a guide about hypertransport and it connects:
CPU's together and the Northbridge to the southbridge.
Therefore faster transfger between the USB and processor etc,

On another point, now they are using this better communication bus in the computer, will they be introducing PCI-X or PCI-64 fully now? So we just have PCI-64 slots.

Imknow they are backwards compatable so I see no reason why they should not. NO doubt creative will release a sound blaster live with 64bit interface. I know Adaptec already make scsi cards which work on this interface.
September 2, 2002 1:54:04 PM

Ahh I see, but if I'm not mistaken, Ch will only have either 2 8bit links, or 1 16bit link. And also, according to hwat I've heard, Opteron will have 3 16-bit links, so it seems the Opteron will really have some nice bandwith for MP setups (CH will probably be locked, and unusable in MP anyways). Then, this means that the only way to solve the bandwith would be to have an FSB that is clocked high (since it seems HT willnot replace the FSB), and that leaves most of the problems to be solved by the on-die mem controller.



- - -
<font color=green>All good things must come to an end … so they can be replaced by better things! :wink: </font color=green>
September 2, 2002 2:32:29 PM

"(CH will probably be locked, and unusable in MP anyways)."

True because the socket will be different, not because of any locks. Unless someone comes out w/ a MP board for CH, you wont be able to use em in a dual config.

This sig runs too hot.
September 2, 2002 2:53:52 PM

Perhaps someone will create a Socket 754 to Socket 917 (I forget the number) converter?

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
September 2, 2002 2:58:08 PM

This is truly nice bandwidth, but are you sure it's that much? It surpasses RDRAM by far and its latency is far less as well, makes you wonder if Intel may not consider that as well...

But the thing is, Dual Channel 128-bit would be extremly costly and hard to make, ya know? And also that would mean with current tech, DDR333 would impose a serious bottleneck of HALF provided bandwidth only, at 2.7GB/sec.
So that means ClawHammers or SledgeHammers even more, will not be having their potential unleashed until DDR II comes out or even QDR... hmm that does sound to be a bit bad, since the performance will be quite lower than what it should be.

After what you said about the HT relaying to everything else, I think it makes sense to say there is no FSB now.
Still that raises the question: How do Hammers clock? And how do Hammers OVERclock?

Finally some interesting news about Hammers, I thought there was nothing but sad stuff about them these days. Only thing remaining is performance.

I still have no answer by anyone, what are the advantages or noticeable advantages HT provides to a normal user, say like me, who surfs, plays, writes stuff?

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
September 2, 2002 4:57:57 PM

You're talking about dual channel DDR333.
Will taht be an other type of DDR333 (the one that's now available) or do we have to put 2 DDR333 sticks. Like the edo used to.

And what about the IRQ? Still 15 or more. I can sure need more since I already used all and still can put 3PCI cards on my mobo.


If I buy the boxed version of the "hammer", will I get a box of nails for free??
September 2, 2002 5:01:33 PM

Actually I think I got the numbers wrong. The Opteron will use a 128-bit DDR333 controller (which is actually a dual channel 64-bit DDR333) for the 5.4 GB/sec bandwith, while the clawhammer will use just the single channel 64-bit DDR333 controller, for 2.7 GB/sec, which is decent but could be better.

Also, in regards to someone elses post, AMD is targetting clawhammer for 1-2 way systems, and sledgehammer for 4+ way systems. So, you will be able to get multi-processor Clawhammer systems.

"Trying is the first step towards failure."
September 2, 2002 5:49:27 PM

Ya, but I meant something else. I forgot to mention there will be <b>two</b> versions of clawhammer. The first version will replace the current Athlon as AMD's flagship. The second version will be the Clawhammer MP which will work in a dual-conifg. It will replace the Athlon MP. What I meant was that I don't think you'll be able to use 2 regular clawhammers in a dual-config. I meant that AMD will probably lock the "single" version of clawhammer, so it won't be usable in dual systems. In other words, AMD will make you get the clawhammer MP to use it in a dual-config. The MP might have different pins than the "single" version, probably as an extra safety measure. Opteron, of course will have a different pin configuration and won't be compatible with clawhammers, since they will be a different class or category of CPU's.

Eden, they could make a converter to convert from different sockets, but I bet it'll be awfully expensive, and I doubt if they can make a converter which would allow a clawhammer to run in an opteron board.

- - -
<font color=green>All good things must come to an end … so they can be replaced by better things! :wink: </font color=green>
September 2, 2002 6:23:03 PM

yeah the versions of the cores are:

Athlon Clawhammer (Single Processor)
Opteron Clawhammer (1-2 Processor)
Opteron Sledgehammer (2-8 Processor)

Clawhammer socket is not compatable with sledgehammer socket. As far as I have read the difference between opteron Clawhammer and Athlon clawhammer is the same as the difference between Athlon XP and Athlon MP.

So a single processor clawhammer does not have to meet the same standards as the multiprocessor versions. (As with the athlon and athlon MP)
September 2, 2002 6:38:01 PM

Quote:
The Opteron will use a 128-bit DDR333 controller (which is actually a dual channel 64-bit DDR333) for the 5.4 GB/sec bandwith, while the clawhammer will use just the single channel 64-bit DDR333 controller, for 2.7 GB/sec, which is decent but could be better.

Clawhammer's initial 2.7 GB/s bandwidth may sound dissapointing in theoritical point of view, but it will be actually faster than today's P4 400 MHz FSB and Athlon 400 MHz FSB (If AMD maxes out EV6 bus). They provide theoritical bandwidth of 3.2 GB/s, but practically it is limited to 2.5 GB/s. Clawhammers on-die memoy controller will use DDR 333 provided 2.7 GB/s bandwidth much more efficiently. Practically CH can get about 2.6 GB/s or little more from DDR333. So it will be practically faster than PC800 RDRAM and DDR400.

IMO, hammer's on-die memory controller is going to be a must in near future for all CPUs like today's on-die L2 cache.
September 2, 2002 6:43:07 PM

Very interesting thread.. All I can say it that im really looking forward to clawhammer. Hopefully memory can take advantage of this new bandwidth.
September 2, 2002 9:14:56 PM

A few things to point out. Clawhammer will have 1 16-bit Hypertransport link to the chipset and a 64-bit memory interface. It may be upgraded in later revisions to DDR-II. Sledgehammer will have a 128-bit memory interface. Sledgehammer will have 3 HT links. Each 16-bit for the interface connecting to the chipset and a 32-bit link for interchip connections IIRC. Each have their own dedicated memory pocket and interface of course.
And yes, the integrated memory controller on the Hammers will cut down on latency significantly and increase actual throughput. However, a 64-bit 166MHz DDR memory interface will provide a maximum of 2.7 GB/sec, even without the memory controller to chipset and chipset to processor interface latency, you'd still have to deal with the memory latency. Let's say that the best case happens and the access latency is 2 cycles. Under normal circumstances, it would take 7 cycles for the first 8 byte critical word to transfer to the CPU from the initial access call and then 3 cycles to transfer another 24 bytes (I'm assuming Hammer memory controllers will use 4x 8 byte cacheline as well). In the case of the integrated memory controller, we can shave off 2 cycles (bypassing the latency normally associated with relaying through the chipset) which means instead of 10 cycles to transfer 32 bytes, it'll only take 8. 32 bytes/8 cycles = 4 bytes/cycle average. This translates into 1.33 GB/sec maximum throughput in the best condition case for DDR SDRAM running at 166MHz DDR. If the memory controller weren't integrated, the memory throughput in the best case would be 1.066 GB/sec. The throughput in the best case would compare to a DDR memory and interface running at 208 MHz roughly, single channel. It still won't compare to a dual channel 133MHz DDR memory interface and memory (Granite Bay).
As for RDRAM. While RDRAM's best-case transfer throughput isn't much higher than 1.33 GB/sec, it does reach its best-case throughput more often (DDR SDRAM does this around 50% of the time I'd guess while RDRAM would probably reach it 70% of the time). This is due to the fact that RDRAM has more buffer banks so that it won't have to suffer from ras or ras to cas delay as much as SDRAM.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.
September 2, 2002 10:39:12 PM

I think we need a new type of Ram, as intel went for rambus, AMD needs to pick a really good ram type.


What I believe is the Hammer series of chips will give even intel a run for their money.
September 3, 2002 12:02:44 AM

Yes, texas_techie is back. I havnt posted here cuz there hasnt been much to report on the AMD front. I got a few tid-bits though.
I gotta say first this is an excellent thread. First time I have seen a discussion that didnt lapse into a flame war.

I think Eden said the only think left to know was Hammer's performance. AMD has been INCREDIBLY stingy with benchmarks. I only know of one. The source is outstanding. But I cant believe the number. The bench was Primordia ( a science benchmark) - and Hammer beat everything out there (yes even the P4 2.8) by about 300%.
I honestly wouldnt put much stock into that until I can find out more. Cuz that sounds WAY to good to me.


2. Saw some preliminary stuff on K9 and even k10. The only thing interesting about either core is the extremely low wattage they are shooting for ( less than half of AMDs current wattages).

-Bye now

Benchmarks are like sex, everybody loves doing it, everybody thinks they are good at it.
September 3, 2002 1:17:20 AM

Texas I wish I had your sources.......

Hmm Maybe when I finish uni, I should try and get a job in AMD R&D.

Anyway lets all sit down and listen to texas Techie

:tongue:
September 3, 2002 2:25:28 AM

Do they like you posting all this top secret stuff? Isn't it under NDA or somthing? :eek: 

<i>Past mistakes may make you look stupid, but avoiding future ones will make you look smart!</i>
September 3, 2002 2:51:54 AM

That's why he keeps it as minimal informing as possible

However texas' news seems pretty nice, it would be near unbeleivable if Hammer can do so much in Science! I know LHG is a big freak into Science benchmarks.

I do hope this goes on with good news, it'd be so nice to finally have true competition like this, return. Not for the Science results but because it is starting to feel rather positive. One can only hope, really.

Though I find it a bit exagerated that they have even K10 plans, I mean that's really far, we're talking like planning two new architectures ahead of the P7 core, kinda!

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
September 3, 2002 4:40:03 AM

Yeah well the stuff on K10 is real sketchy, premilminary kinda stuff. Im sure it will change a million times. I think they were shooting for late 2004 on k9 - with k10 to follow VERY shortly after that. Gonna be interesting.

Honestly, the way things are going - I wouldnt expect to see any benchmarks in the near future from me. They are about as easy to get as a presidential pardon.

Benchmarks are like sex, everybody loves doing it, everybody thinks they are good at it.
September 4, 2002 8:29:57 PM

Hmm usually core switches seem to go by 3 year increments, to release a K9 in 2004 would be rather short and make the K8 buyers pretty pissed if no upgrade paths are open. And stating K10 would follow shortly after is a very bad bobo!
But anyway they will change a million times as you said, which has always been true, so I expect these figures to be drastically different from what you said here.

--
When buying an AthlonXP, please make sure the bus is at 133MHZ, or you will get a lower speed!
September 4, 2002 9:24:28 PM

I am sure intel have several generations of pentium planned just like AMD with their chips. The thing is that the size of the team working on a K10 core would be much smaller than that working on the K8 core.

Maybe a K9 or K10 core is gonna use a 0.065Micron?

Anyway, does texas work for AMD?
September 5, 2002 1:46:19 AM

Holy [-peep-] if that 300% estimate is ANYWHERE near accurate, then hammer is really going to be great.. All I can do is hope, I dont have much money to spend on sutff like computers, so thats why im generally an AMD fan, unless Intels performance/price gets better thans AMDs, then ill be an AMD guy. I will admit right now that for pure power, Intel is seriously beating out AMD.
September 7, 2002 7:08:03 PM

You're kidding me right? AMD shooting for low wattage on K9, and K10? Wow, Intel is doing the same thing. With their core-hopping technology, hyperthreading, BBUL packaging, their implementation of SOI, as well as their 0.65 process, Intel is really concentrating on low heat/wattage.

I also doubt the release dates you speak of for K9/K10. IF they are true, then the core revisions won't be that major.

- - -
<font color=green>All good things must come to an end … so they can be replaced by better things! :wink: </font color=green>
<P ID="edit"><FONT SIZE=-1><EM>Edited by Dark_Archonis on 09/07/02 03:08 PM.</EM></FONT></P>
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