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Trade-off in hammer or any integrade MCH

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September 26, 2002 11:08:50 AM

DMA just think about it.

If the PCI need to access the RAM all data will have to go to the CPU via HT and to controleur and to the ram at last it a must slower process.

At the end i have speak with a horny lady

More about : trade hammer integrade mch

September 26, 2002 5:32:58 PM

With 3 Hyper Transport links I doubt the processing unit will even hiccup. Sure it will still have to compete for the resource, but that's what the Crossbar (Xbar) communications architecture is for. With 1600 Mega Transfers a second and 3.2 GBs in each direction, even the hungriest PCI device will be satisfied. When AGP 16x comes out this system may be strained but that's a long way off.

EDIT Replaced 16000 Memory Transfers with 1600 Mega Transfers

Complicated proofs are proofs of confusion.<P ID="edit"><FONT SIZE=-1><EM>Edited by Schmide on 09/26/02 03:51 PM.</EM></FONT></P>
September 26, 2002 5:45:21 PM

Not a problem. Functionally, it's no different than having the MCH off-die--it's just a different routing of traces. All other things being equal, there's no reason why an off-die MCH would perform any better.

<i>I can love my fellow man...but I'm damned if I'll love yours.</i>
September 26, 2002 6:31:17 PM

The HyperTransport/Memory controler is acsessed w/o any CPU intrevention. so the going through the integrated MCH or HyperTransport is just like a any northbridge...

Quote:

If the PCI need to access the RAM all data will have to go to the CPU via HT and to controleur and to the ram at last it a must slower process.

Today if the PCI (southbridge) needs acsess to RAM - it goes through the SouthBridge->northbridge interconnect (like VIAs vLink) to the memory controler. there is no diffrence if it is on the CPU or else. (accept that HT provides more bandwith from regular interconnects and the MCH less latncy).


This post is best viewed with common sense enabled<P ID="edit"><FONT SIZE=-1><EM>Edited by iib on 09/26/02 09:33 PM.</EM></FONT></P>
September 26, 2002 9:19:12 PM

Dude, you're taking about the Opteron when you refer to 3 HT links. Clawhammer only has 1 link. According to what I know, the MCH on Hammer works independently of the CPU. SO, I doubt that it will be a problem. Also, If I'm not mistaken, the north-south interconnect WILL NOT be PCI, but HT itself.

EDIT: the north-south interconnect will only be HT on AMD chipsets, as far as I know. So, different chipsets may use different interconnects, unless AMD forces evryone to use HT as a north-south interconnect.
- - -
<font color=green>All good things must come to an end … so they can be replaced by better things! :wink: </font color=green>
<P ID="edit"><FONT SIZE=-1><EM>Edited by Dark_Archonis on 09/26/02 05:22 PM.</EM></FONT></P>
September 26, 2002 9:53:01 PM

True the Claw will have only 1 HT link. That doesn't make a difference in the numbers, as you only need one HT link to sustain 3.2 GBs asynchronous transfers. 32 bit pci runs a whopping 60mb a second. That's 1.8 % of the bandwidth of HT. 64 bit pci breaks the 240mb rate. We're now up to 7.5% of the bandwidth of HT. AGP 8x starts to break the bank at 2.1GB as second. Now that's 68% of the bandwidth. All of witch run synchronously

Complicated proofs are proofs of confusion.
September 26, 2002 10:08:54 PM

higher lantency for storage, for server that a big hit for a big gain on RAM front it also load the memory controleur bus for nothing, like everything there a trade off.

That wierd i sure some have see this but not mention about it.

At the end i have speak with a horny lady
September 26, 2002 11:02:59 PM

There is no trade-off.
<b>a southbridge CAN NOT acsess the RAM on any chip-set</b> today. it acsess the NorthBridge through an interconnect (like VIA's 533Mhz VLINK).
nothing changes when the northbridge is on-die.


This post is best viewed with common sense enabled
September 26, 2002 11:05:45 PM

Quote:

Sure it will still have to compete for the resource

Today it also "competes" for resource - becouse <b>SouthBridges CAN NOT acsess RAM</b> they go through the NorthBridge.

This post is best viewed with common sense enabled
September 26, 2002 11:27:53 PM

Higher latency than what milliseconds? Remember hard drives have latencies of milliseconds. That's an order of a 0.001. So if I do the math correctly. HT operates at a maximum speed of 800mhz, which gives it a minimum latency of 0.00000000125 or 1.2 nanoseconds and operates at a minimum of 200mhz, which gives it a maximum latency of 0.000000005 or 5 nanoseconds. PCI buses run at 33mhz, which gives them a minimum latency of 300 nanoseconds. PCI 64 buses run at 133mhz, which gives them a minimum latency of 75 ns. AGP busses run at 533, which give them a minimum latency of 1.8 nanoseconds. I don't think HT has anything to worry about.

Summarizing latencies
0.00000000125 HT best
0.0000000018 AGP
0.000000005 HT worst
0.000000075 PCI64
0.000000303 PCI
0.00000125 ISA
0.005 A very good drive.

Edit made a mistake on AGP

Complicated proofs are proofs of confusion.<P ID="edit"><FONT SIZE=-1><EM>Edited by Schmide on 09/26/02 04:34 PM.</EM></FONT></P>
September 26, 2002 11:57:52 PM

Quote:

EDIT: the north-south interconnect will only be HT on AMD chipsets, as far as I know. So, different chipsets may use different interconnects, unless AMD forces evryone to use HT as a north-south interconnect.


Actually, the nVidia chipsets also use hypertransport. SiS has licensed it to incorporate it in future chipsets and to be better able to connect to Hammer via hyertransport.

Not sure about VIA or ALi

Mark-

<font color=blue>When all else fails, throw your computer out the window!!!</font color=blue>
September 27, 2002 12:56:54 AM

if you say so

At the end i have speak with a horny lady
September 27, 2002 1:56:07 AM

Why do you guys ignore my posts?
Becouse they make this whole argument invalid?

<b>Here are the FACTS:
Today: southBridge acsess memory through the northbridge. the southbridge and northbridge are connected through an interconnect.

Hammer: southbridge still acsess memory through the northbridge. using an interconnect (HyperTransport).

There is no diffrence.
</b>

Southbridge was never capble of acsessing RAM. only the northbridge has a memory controler which handles memory acsess.

This post is best viewed with common sense enabled
September 27, 2002 2:15:53 AM

Ahh the attention craving, yeah it's weird once you state the obvious, some may not reply! Only picky ones like imgod2u and Slvr will find little flaws to correct!

One question, that still until today remained unanswered to me: What are going to be the NOTICEABLE advantages of HT in a normal user's workaround? Like me, as a normal user, what would using the Hammer paltform with HT bring? I can clearly see it has almost all advantages you want, and that it's clearly a very impressive and fast technology, but what are the Noticeable things, for normal users, and also if possible, the workstation and server market?

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September 27, 2002 2:55:44 AM

iib I agree with everything you said. Thus you get the last word on those topics.

Hyper Transport is a proven technology. However, we do not know at what speed it will run on the final Hammer processor. We do know that it will have 16bits, so it will max out at 6.4GBs at 800mhz. A 32bit implementation will max out at 12.6GBs. I good read is <A HREF="http://www.hypertransport.org/faqs.html" target="_new">here</A> and especially <A HREF="http://www.hypertransport.org/faqs.html#q26" target="_new">here</A> for comparisons on existing technologies.

Complicated proofs are proofs of confusion.
September 27, 2002 3:10:51 AM

For the desktop user it won't bring much. it will replace current interconnects but those we're already suffecent for home use.
Under Server/Rorkstation envirment HT brings about a few advantages:
1. more bandwith between NB and SB for demanding workstations.
2. this is the interconnect that allows Hammer multi processing design. this is really a big topic which I can't cover.
3. HyperTransport brings "Lego like" system design - AMD slides showed a varty of system utilizing direct connections between processor and other ICs (integrates circuits AKA "chips" ;)  ) to have a specific functions - such as HyperTransport compatible SSL incryption processors for web-servers. other design shown are for TCP offloading, storage servers, uniqe assymtrec multi processing systems. such "Coustom built" systems could be very strong for there praticular task utilizing HyperTransport compatible chips - this is why AMD trys to bring the whole indestry behind HyperTransport.

I feel the 2nd and 3rd reason is the "real" blow Hammer will deliver. this flexabilty in Hammer system design can edge other processors for specific task - at a much lower cost: there is no need for costum chip-sets or any complemtry IC in MP designs. less need for large on die cache sence memory acsess isn't shared by all processors togther (each has its own memory controler) - SledgeHammer will have a die size of ~200mm - that is less the willmate and far smakker then expensive ~400mm Itanium, Alpha, Power, SPARC etc... adding coustom ICs for praticular tasks I think will allow Hammer to edge a most other systmes with still a lower cost.


This post is best viewed with common sense enabled<P ID="edit"><FONT SIZE=-1><EM>Edited by iib on 09/27/02 06:12 AM.</EM></FONT></P>
September 27, 2002 11:42:02 AM

http://www.amd.com/us-en/assets/content_type/white_pape...


Opteron main boards layout

1 PCI or IDE to South bridge
2 South bridge to AGP hyper transport or PCI-X hyper transport
3 AGP or PCI-X to CPU
4 CPU to RAM or a others CPU
5 Finish or a others CPU or RAM
5 finish or RAM

vs

PCI to south bridge
South bridge to north bridge
North bridge to RAM


At the end i have speak with a horny lady
September 27, 2002 6:12:18 PM

What are you saying? Before you draw any conclusions, remember if you have a chain of communication, your transmission rates (throughput) will always be equal to your slowest link. Your transmission latency will equal the sum of all link latencies. Sure there are some differences in routing, but that in no way justifies the FUD you are trying to spread.

Complicated proofs are proofs of confusion.
September 27, 2002 6:13:46 PM

First of all there are only 3 complemntry ICs to Hammer:
AGP*3 Graphic tunnel.
PCI-X Tunnel.
I/O Hub.

Desktops wont use PCI-X tunnel. Only servers workstations will. so its 4 parts top.

Secondly - you have a very limted view of "cost".
Hammer is an almost ZERO R&D product - sence you dont need to devlopt ANY chip-sets for it. if IBM/HP/SUN want to adopt hammer - they won't need to devlopt any chip-sets for it nor buy them from ServerWorks/Intel. it is all on die - all you need to do is <b>Print a mobo for your system</b> wheater its 4CPU or 32CPU systems - all you need is to print the PCB and circiuts and place Hammer in the sockets. Hammer flexabilty makes for a very low cost system design. you use the same parts wheater its a 2way server or a 32way server - no need to devlopt chip-sets to support it.

This post is best viewed with common sense enabled
September 27, 2002 10:57:34 PM

What are you saying? Before you draw any conclusions, remember if you have a chain of communication, your transmission rates (throughput) will always be equal to your slowest link

That for bandwith it not a trouble on hammer on mainboards.

Your transmission latency will equal the sum of all link latencies

True

Sure there are some differences in routing, but that in no way justifies the FUD you are trying to spread.

I dont say that the PCI performance will drop by 1000% but it will be a slower that normal MCH



At the end i have speak with a horny lady
September 27, 2002 10:58:18 PM

I have also say this will happen also on EV7 Marvel

At the end i have speak with a horny lady
September 27, 2002 11:57:34 PM

Quote:
I dont say that the PCI performance will drop by 1000% but it will be a slower that normal MCH

You or none of us can say it will be faster or slower than any other system out there. If you can explain why you feel it will be slower, that would be a constructive argument. The fact is HT has more than enough bandwidth and an extremely low latency that it could out perform any know solution already out there. We just don't know. The raw figures point to better performance.

Why <font color=red>exactly</font color=red> do you believe it will be slower?

Complicated proofs are proofs of confusion.
September 28, 2002 12:49:31 AM

The Hammer does use chipsets. The only thing for the Hammer that is on-die is the memory controller. You still need a chipset for controlling everything else in the system.

<A HREF="http:// http://www.tomshardware.com/cpu/02q2/020424/opteron-03.... " target="_new">http:// http://www.tomshardware.com/cpu/02q2/020424/opteron-03.... </A>

Not only does AMD have their chipsets for it, but other companies like SiS, VIA, ALi, and nVidia are also making their own chipsets for Hammer.

-------------------------------------------
<font color=blue> "Trying is the first step towards failure." </font color=blue>
September 28, 2002 1:46:01 AM

Soon we will able to bench that springdale vs Hammer Intel will have a advantage they have better driver and implemtation.

Wich i say that DMA is not a DMA any more that will need to be rework and others.

At the end i have speak with a horny lady
September 28, 2002 3:03:15 AM

Quote:
Soon we will able to bench that springdale vs Hammer Intel will have a advantage they have better driver and implemtation.

So I take it from this last comment. Your motivation here is to tout Intel and not discuss the benefits/hindrances of the Hammer platform. Ah how your true colors show. Zealot.

Complicated proofs are proofs of confusion.
September 28, 2002 3:37:48 AM

LOL

I have strat speaking from integrade MCH hammer or any others hammer was the reference because most of the useur here know AMD/intel X86.

I have start from a tecnical stant point wich have turn very fast to flame war after someone have move this to benchmark wich take in accounth driver impletation south bridge mobo.I dont have made that you have do to protect your hammer form any harm it can get.Get real AMD is lag behind intel on every point.INTEL have allready made the move from ILP to TLP X86 ro VLIW huge advantage on manufacturing process.

At the end i have speak with a horny lady
September 28, 2002 3:39:32 AM

We're not discussing who's ahead, we're discussing a certain interesting technology, that's all, it's harmless dude!

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September 28, 2002 4:28:19 AM

If you read back through the posts, just look at who talked about technology and who talked about Intel vs AMD, you'll know who's searching for a flame war. I called you on it. It's as simple as that.

I never mentioned any other technologies specifically. I stay on topic and search for information before I post. You approach everything with a bias favoring Intel and always look for flaws in AMD. Every prediction I made was based on figures and information. I back up what I say and am never afraid of being proved wrong. I like to draw varying conclusions, as you like to predict the future in concrete terms. I'm sorry if you think I flamed, but I call a Zealot when I see one and I doubt you came here to actually discuss the possibilities of AMD's next product. I quote

Quote:
Get real AMD is lag behind intel on every point

Complicated proofs are proofs of confusion.
!