CPu scaling vs DRAM scaling

[juin]

I take the athlon for puporse becasue that a much older CPu also make the bridge to P4/RDRAM.There is no benchmark or no AMD vs intel.

When athlon has been release.

500 mghz 800/mbs mghz ram a good team alomost 1 bit by Flop
700 mghz 1/gbs mghz ram a good team also
1200 mghz 1.6/gbs mghz ram a good scale
1333 mghz 2.1/gbs mghz ram a good scale
2225 mghz 2.7/gbs mghz ram where is the RAM now
Hammer 2XXX mghz 2.7/gbs


P4

2000 mghz 3.2/GBS
2.53 mghz 4.2/GBS
3.XXX mghz 5.4/GBS
5.XXX mghz 6.4/GBS

Opteron
1XXX mghz 5.4/GBS

Itanium 2

1000 mghz 6.4/GBS

Server chip have good memory controleur and good balance.Itanium mobo must so hard to built due to is 256 bit path.This is a mobo not a PCB of a graphic card.

Athlon/P4/P5/Hammer

Lantency in clock cycle increase not decrease and each times you growth cache there a good chance that you add clock cycle lantecy.Like Presscott may have a 8 clock cycle lantecy ulike NW/willi at 7 that a direct hit to FPU.Clawhammer stay on 256KB L2 may lantency time unknow around 7 clock.

Bandwith increase with more channel in 2005 we will need a 256 bit path on desktop 1024 bit path on server.This badly increase cost.Forgot about RDRAM it dead or almost unless a new chipset and new R&D at samsung.

With a 3.5 hammer we will get a DDR 2 for 3.2/GBS with slower internal timing.
With a 5 GHZ P4 presscot DDR-2 dual channel a 6.4/GBS.

We can have more bandwith but a t a higher price but it dont help on lantency.SO it will be more cache and more cache by increasing die size power consumation.

Now what to do??

 

[imgod2u]

Server chip have good memory controleur and good balance.Itanium mobo must so hard to built due to is 256 bit path.This is a mobo not a PCB of a graphic card.

Itanium 2's use a 128-bit data path to memory.

Lantency in clock cycle increase not decrease and each times you growth cache there a good chance that you add clock cycle lantecy.Like Presscott may have a 8 clock cycle lantecy ulike NW/willi at 7 that a direct hit to FPU.Clawhammer stay on 256KB L2 may lantency time unknow around 7 clock.

Northwood/Willamette has a 3 cycle latency L2 cache.

Bandwith increase with more channel in 2005 we will need a 256 bit path on desktop 1024 bit path on server.This badly increase cost.Forgot about RDRAM it dead or almost unless a new chipset and new R&D at samsung.

You should take a look at Yellowstone. Although it may not ever hit the market it is still an interesting idea. Not to mention you could always refine technology to scale higher in frequency, not neccessarily having to increase the width of datapaths.

We can have more bandwith but a t a higher price but it dont help on lantency.SO it will be more cache and more cache by increasing die size power consumation.

Technology does not remain stagnant. As we progress towards the higher need for faster memory, process refinement and new technologies will come out to meet that need. The same goes for SRAM in caches. Today's MPU's go in excess of 50 million transistors, and cost less than MPU's back in the days with less than 10 million transistors. Why? Because processing technology improves and manufacturing costs diminish with volume sales.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[juin]

Itanium 2's use a 128-bit data path to memory.

128 bit FSB 256 bit memory also know as Quad channel DDR Pc 1600 (2100 for HP) Ready for 133 mghz FSB ???

Northwood/Willamette has a 3 cycle latency L2 cache

Sorry that it lower that athlon L1 P4 have 7 clock latency

You should take a look at Yellowstone. Although it may not ever hit the market it is still an interesting idea. Not to mention you could always refine technology to scale higher in frequency, not neccessarily having to increase the width of datapaths

Rambus once again even rambus say this will not get to DRAM market.RDRAM 64 bit lose is indepandant adress row capacitie to share mode to save some space.

Technology does not remain stagnant. As we progress towards the higher need for faster memory, process refinement and new technologies will come out to meet that need. The same goes for SRAM in caches. Today's MPU's go in excess of 50 million transistors, and cost less than MPU's back in the days with less than 10 million transistors. Why? Because processing technology improves and manufacturing costs diminish with volume sales.

Madison vs mackinley

only cache change but if there were faster memory we can use this 300 million tansitor to add others feature or reduce power cosumation.It will be really hard to keep the low lantency 11 clock cycle on L3 maybe they have donne it but nothing it sure that the same will happen when moving 12 mb L3 add few cycle also we allready pre-fecht adding overhead and sometimes waste bandwith.We really need faster memory with low pin count from jedec so every is happy.

Now what to do??

 

[imgod2u]

128 bit FSB 256 bit memory also know as Quad channel DDR Pc 1600 (2100 for HP) Ready for 133 mghz FSB ???

It isn't utilized by 1 CPU. The CPU actually has a 128-bit data path, it merely goes to a hub with dual banked ram.

Sorry that it lower that athlon L1 P4 have 7 clock latency

Official word is that it's 7 cycles, however, it is pipelined so new data is transfered every 2 cycles and sustained data rate is transfered every cycle. Realistically, it usually comes out to 3 cycles per data transfer.

Rambus once again even rambus say this will not get to DRAM market.RDRAM 64 bit lose is indepandant adress row capacitie to share mode to save some space.

I was not aware of any official word from Rambus on this.

Madison vs mackinley

only cache change but if there were faster memory we can use this 300 million tansitor to add others feature or reduce power cosumation.It will be really hard to keep the low lantency 11 clock cycle on L3 maybe they have donne it but nothing it sure that the same will happen when moving 12 mb L3 add few cycle also we allready pre-fecht adding overhead and sometimes waste bandwith.We really need faster memory with low pin count from jedec so every is happy.

The excessive caching of Madison really has to do with the design of the second generation IA-64 processor rather than a reliance on memory to in general. Being an in-order-execution processor, Madison/McKinley relies on a huge amount of fast-access memory in order to keep itself busy. That is not to say later revisions can't be out-of-order execution and hence alleviate some of the dependence on cache. And memory technology is indeed scaling. DDR-2 is supposed to have many features that would help in scaling of frequency while using the same 64-bit data path. Not to mention the future may include QDR memory.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.