P4 QDR bus, wtf?

[Col_Kiwi]

I know what QDR is, i know how P4's bus has it, and i know it means 4x data bandwidth. I started thinking about it more in-depth and realized it doesn't add up for me.

Allow me to give some examples:

PCI:
32-bit wide bus / 8 (bit -> byte conversion)
=4 bytes/cycle
4b/c * 33MHz
=133MB/s

Now with a multiplier.

AGP 2x:
32bit wide bus / 8
= 4 bytes/cycle
4b/c * 2 bits per path per cycle (2x)
=8 bytes/cycle
8b/c * 66MHz =
533MB/s


So thats how i'm explaining bus transfer rates to myself. (correctly?). But P4's bus is where it gets confusing...

32-bit wide bus / 8
=4 bytes/cycle
4b/c * 4 bits per path per cycle (QDR)
=16bytes/cycle
16b/c * 100MHz
=1.6GB/s?!

Its 3.2GBs according to intel... what did I calculate wrong?

If you read their website, they specify 128-bit bus, which you could most likely interpret as them multiplying the QDR factor in beforehand.

128bit wide bus /8
=16bytes/cycle
16b/c * 100MHz
=1.6GBs...

still makes no sense.

And if you assume that its 128 bit and THEN multiplied out for QDR, you get a way too large number..

128 / 8
=16b/c
16 b/c * 4 (QDR)
=64bytes/cycle (whoa!)
64bc * 100MHz
=6.4GBs...
That's not right either.


What math am I forgetting? Does Intel have some technology I'm forgetting? What? This is bugging me.

Thanks for any insight.


-Col.Kiwi

 

[Crashman]

The CPU bus is 64-bits wide. This may sound confusing for a 32-bit processor, but it's true.

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[eden]

Yup, it uses a 64-bit bus with quad signaling, which I also have trouble imagining, while DDR is much easier to think up. Actually on a pure SDR bus, P4's bus is 256-bits wide.

64-bit is 8 bytes. 100MHZ times 8 is 800MB, times the Quad pumping, equals 3.2GB/sec. If we eliminated quad pumping and were so crazy as to pump the data path and make costs so huge, it'd be 256/8= 32, 32 times 100MHZ SDR= 3.2GB.
There is a difference between bitpaths and data rates, one being the width of the carrying, the other is how many of these you can put in one clock wave. (Imagine a sea wave, imagine in 2d, it looks like a triangle, almost, put on each side except the bottom, 8 bytes, there's your DDR. QDR, I still don't get, and even long explanations won't help, I seriously need a video to get it.

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[imgod2u]

Make sure they're refering to the P4. Itanium 2 uses a 128-bit bus to the memory hub.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[Col_Kiwi]

@#$%!! asoufbasrigbaskrejtb!

I can't believe I didn't think of that. Thanks.

I assume that means that "32 bit processor" is actually referring to the instruction set size, and having a 64 bit bus is for the sake of avoiding bottlenecking?

-Col.Kiwi

 

[Crashman]

Right, the 32-bits is just the instruction set, data pathways have been 64-bit ever since the Pentium 1.

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[imgod2u]

No, "32-bit" refers to the size of the General Purpose Registers (GPR). The GPR's are little pockets of memory where single data types are stored (any of the 3 data types that CPU's handle, be they FP, integer or memory address). It has nothing to do with the instruction set. It has to do with how big a single piece of data can be that the processor is doing work on.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.