I've been seeing a few questions on 64 bit cpu's and memory addressing lately; some people ask why itaniums and Hammer are "limited" to 40 or 48 bit memory addressing instead of the 64 you'd expect. I made some calculations I'd like to share with you:
*) 36 Bit addressing as supported In theory by current Xeons (Athlons ?)using a few hacks, allows up to 64 GB of memory.
*) 40 bit, which is the limit of physical addressable memory for both Itanium and Hammer I think, allows for 1024 GByte. That is a pile of +-3meter high of 1 GByte Dimms. Try and install that in a 4U rack !
*) with 48 bit addressing, that same pile of 1 GByte Dimms becomes 1,5 times as high as the WTC was (+-780 meters)
*) 64 bit allows up to 16 billion gigabyte, which would make that same pile no less than 52 thousand kilometers high. To give you an idea, the space shuttle orbits at an altitude of around 200 kilometer
*) some dork suggested 128 bit addressing. That would result in a pile 100.000.000.000.000 lightyears high ! Yes, LIGHTYEARS. The approximate mass would be 3.000.000.000.000.000.000.000.000 tons (estimating 10 gramms/dimm).
Calculations done assuming 3mm for a double sided DIMM.
So, 48 bit memory addressing will do for a while, no ?
(please note, im not saying there is no practical use for 64 bit computing, Im purely talking about addressable memory here).
= The views stated herein are my personal views, and not necessarily the views of my wife. =<P ID="edit"><FONT SIZE=-1><EM>Edited by bbaeyens on 10/17/02 03:12 PM.</EM></FONT></P>
Don’t forget its frikkin slow after the 4 gig barrier somewhere in the range of 10 to 100 times slower than normal memory use PAE is a novel idea but limited severely by the speed of it. And with AWE being used individual processes on 32bit CPU’s still can’t exceed 4 gigs. Hence why 64bit CPU’s have been so popular for science, aerospace, and automotive just to name a few examples.
<font color=blue>Just some advice from your friendly neighborhood blue man </font color=blue> :smile:
juin you are so far off. All. Let me emphasize "ALL" processor since the Pentium Pro can address 2^36 bytes of memory. You must enable a flag in the PAE (Physical Address Extension) or use the PSE (Page Size Enable) in CR4 on Pentium III+ processors.
See chapters 3.8 and 3.9 of the Intel IA-32 software developer manuals.
Well, something I should point out is that physical address extension is not slower "after the first 4 GB". It's slow to switch from the first 4 GB block to the next block. However, after your OS is done switching, it's just as fast as the rest of the memory.
"We are Microsoft, resistance is futile." - Bill Gates, 2015.
>You're assuming that RAM density isn't going to change.
No I am not. when I checked, 1GB dimm where the highest density ECC memory modules I could find. 64 bit cpu's are a reality *now*. 40/48 bit addressing is a reality now.
Besides, even with hypothetical (future) 1 Terabyte DIMMs (1000 gigabyte) that pile would still be 52 kilometers high when using the full 64 bit addressing capability. 48 bit addressing might perhaps be maxed out in theory with those terabyte DIMMs, a stack of nearly 1 meter of these uber monster DIMMs. I guess by the time these modules hit the shelves, Itanium12 will be out, as would the AMD K21..
I guess you get the idea..
= The views stated herein are my personal views, and not necessarily the views of my wife. =