Will Hammers have on-die memory controller?

Before reading THG first hammer mobo aricle, I was sure that Hammers are going to use on-die memory controller. But we are seeing a northbidge chipset. If hammer uses on-die memory controller, so why we will need northbridge chipset? Also I knew that hammers will have no FSB. But after reading this mobo article, it seems hammmer will have traditional FSB.

Have AMD changed their mind and going to make hammer without on-die memory controller?

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  1. Even though hammer will have an on-die memory controller, that doesn't mean that chipset manufactures can't come up with their own memory controller solutions. For example, they can add dual-channel ddr support to their Athlon DT (clawhammer) chipset.

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  2. The problem, of course, is that you're still either gonna have to feed the chip via the memory channel on the chip or the HT link. Either one doesn't saturate dual channel DDR. And if you use the HT link, you'll pretty much tie up the bandwidth needed to communicate with the rest of the computer.

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  3. Northbridge doesn't just contain the memory controller, it also contains memory interface to rest of the system (AGP, PCI, etc.) This gives the CPU direct access to the memory, rather than having to go through the northbridge. The other components wills still need a way to access memory, hence you still need a northbridge. Also, a northbridge can still be used as a memory controller for the CPU, if a new memory technology comes around that will perform better than DDR+on-die controller, like DDR-II.

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  4. Ya but the point is how will you get that much memory bandwidth to the CPU? It's another case in which the CPU's memory interface is not as fast as the memory it's paired with. You can either go through the default memory interface (which I'm not even sure you can seeing hows the memory is reserved per chip) or through the HT link which isn't that much bandwidth to begin with.

    "We are Microsoft, resistance is futile." - Bill Gates, 2015.
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