AMD XP vs. Pentium 4 front side bus speed

How come AMD's FSB speed is only 266 MHz and Intel's is 533MHz? Are the speeds comparable to each other? Is it just that AMD and Intel measure the speed differently? I am doing a project for school on comparing the P4 line and Athlon XP line to each other in general. If anyone knows what's up here, knows a good website I can go to, or needs more info, please post. Thanks.
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    Learn about CPUs, cache, pretty much anything.

    The reason for the bus bandwidth, is that the P4 needs more bandwidth than the AthlonXP does at the same clock speed. The AthlonXP is also very efficient in the data throughput and thus it does not need twice more like the P4.

    The worst of enemies shall be prone to later be the best of friends. -Eden
  2. Thank you so much for your help!
  3. I forgot to add, the left link called "CPU theory and praxis" takes you to learn about the architectures with in-depth explanation.

    The worst of enemies shall be prone to later be the best of friends. -Eden
  4. Both are actually 133fsb. The difference is.AMD is DDR or Double Data Rate(2x). It sends data twice per cycle.

    Intel has QDR or Quad Data Rate(4x). It sends data 4 times per cycle.

    So in reality both run at 133fsb. 266 and 533 are just marketing numbers. The general public sees a large number and believes it is actually running at that speed.

    I aint signing nothing!!!
  5. Well, quad-pumping the signal does make it near-effectively 533. I.e. it will transfer as much data per second (not accounting for latency or access commands) as a 533MHz FSB. The difference being you don't actually have to clock it that high (which is very hard to do with a 64-bit trace path).
    Also, as I've mentioned in other posts, the P4 does not neccessarily need more bandwidth than the Athlon on a per-clock basis. Rather your average P4 is usually much higher clocked than your average Athlon and the clock disparity between the processor and memory bus make it neccessary for the prefetch logic to be very aggressive (which takes up memory bandwidth) when fetching cachelines. There's also the reason of the P4 having a bigger cacheline than the Athlon, so every memory access transmits more data from memory even if only 1 instruction out of that entire chunk of data that was transfered is used (albeit a rare case, it does happen in code that doesn't have very good spacial locality).

    "We are Microsoft, resistance is futile." - Bill Gates, 2015.
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