What method was used to increase the bandwidth between the AGP bus and the processor when moving from 4x to 8x AGP?
I thought I remember reading somewhere that the bus speed was increased from 66MHz, to 100MHz, to allow approximately 2GB per second, instead of 1GB. But if that is true, why is it, that all of SiS' 74x series that have 8x, are all 66MHz, not 100?
Or was some other method used for increasing the bandwidth, such as widening the bus?
All AGP is at 66mhz but transfer data multiple times per clock (much like DDR memory). So 2x is twice per clock, 4x is four times, and 8x is eight times. I think.