Defender troubleshooting problem

[Guest]

Archived from groups: rec.games.video.arcade.collecting (More info?)

I've got a couple of Defender machines - neither working, and am having trouble
getting either of them to work.

Voltages are all good at the chips. I've done the -5/+12 mod so I can run 4164s
in the board instead (and I've verified the voltages at the chips and they're
all OK!), but the symptoms described below occurred even before I did the 4164
RAM swap.

The !RESET signal @ the 6809 oscillates at a rate of about 4Hz. Obviously it's
not getting very far. ;-( *BOTH* Boards do the same thing.

Pin 9 of the AND gate @ 6O is high, and it's pins 10 and 11 that are toggling @
4Hz. Tracing that back to the counter @ 5O, the output of Q1 (pin 6) is
oscillating. Pin 2 of the 74393/5O (CL) is low, and the clock input is
oscillating at a much higher rate than pin 6 of 5O.

It all seems kinda odd that it's allowing that /16 clock to get fed through to
the gates that control the reset. Shouldn't pin 2 of the 74393 (clear line) be high?

Anyway, if anyone has any thoughts as to how to proceed, I'd appreciate it!

-->Neil

 

[Guest]

Archived from groups: rec.games.video.arcade.collecting (More info?)

Neil Bradley <nb_no_spam@synthcom.com> wrote:
: I've got a couple of Defender machines - neither working, and am having trouble
: getting either of them to work.
:
: Voltages are all good at the chips. I've done the -5/+12 mod so I can
: run 4164s in the board instead (and I've verified the voltages at the
: chips and they're all OK!), but the symptoms described below occurred
: even before I did the 4164 RAM swap.
:
: The !RESET signal @ the 6809 oscillates at a rate of about 4Hz.
: Obviously it's not getting very far. ;-( *BOTH* Boards do the same thing.

4Hz watchdogging on williams games is pretty standard when the watchdog
is never being kicked. You cal cit the split pad near 3D to disable to
watchdog if you think that's the problem, but it's probably not.

You sure your ROM board is good? If the decoding there is hosed, it'll
keep the CPU board from doing anything.

: Pin 9 of the AND gate @ 6O is high, and it's pins 10 and 11 that are
: toggling @ 4Hz.

Of course... Pin 9 is the power-on reset, 10/11 come from the watchdog.

: Tracing that back to the counter @ 5O, the output of Q1 (pin 6) is
: oscillating. Pin 2 of the 74393/5O (CL) is low, and the clock input is
: oscillating at a much higher rate than pin 6 of 5O.

....of course... The 393 is a free-running counter, and if the watchdog
isn't triggered within 16 counts of the video counter (60 hz, which is
why you're seeing 60Hz / 16 ~= 4Hz resets) then the CPU is reset.


: It all seems kinda odd that it's allowing that /16 clock to get fed through to
: the gates that control the reset. Shouldn't pin 2 of the 74393 (clear line) be high?

It should go high and clear the counter only when 0011100x is written
to address C3FF, which isn't happening since the code isn't running (or
perhaps because 5K or 5M is bad, but that's unlikely...


--
Mark Spaeth mspaeth@mtl.mit.edu
50 Vassar St., #38.265 mspaeth@mit.edu
Cambridge, MA 02139
(617) 452-2354 http://rgvac.978.org/~mspaeth

 

[Guest]

Archived from groups: rec.games.video.arcade.collecting (More info?)

Mark C. Spaeth wrote:
> Neil Bradley <nb_no_spam@synthcom.com> wrote:
> : I've got a couple of Defender machines - neither working, and am having trouble
> : getting either of them to work.
> :
> 4Hz watchdogging on williams games is pretty standard when the watchdog
> is never being kicked. You cal cit the split pad near 3D to disable to
> watchdog if you think that's the problem, but it's probably not.

(light bulb goes on) - *OH* - That makes *TOTAL* sense! I've just never seen a
watchdog circuit like that before! Thanks!

> You sure your ROM board is good? If the decoding there is hosed, it'll
> keep the CPU board from doing anything.

I'm not sure the ROM board is good (and the ROMs, too). That's probably where I
should look first. ;-| That or the decoding logic. Makes perfect sense - if it
can't execute code, then it'll watch dog!

> : It all seems kinda odd that it's allowing that /16 clock to get fed through to
> : the gates that control the reset. Shouldn't pin 2 of the 74393 (clear line) be high?
>
> It should go high and clear the counter only when 0011100x is written
> to address C3FF, which isn't happening since the code isn't running (or
> perhaps because 5K or 5M is bad, but that's unlikely...

I will check that as well - thank you very, very, very much!

-->Neil