Did anybody read <A HREF="http://www.anandtech.com/showdoc.html?i=1600&p=1" target="_new">Anand's report on Cebit, Part II</A>? And did anybody notice on <A HREF="http://www.anandtech.com/showdoc.html?i=1600&p=4" target="_new">page 4</A> of that article? I did, and I saw this:
<i>"SiS's Pentium 4 chipset SiS655 was also first to be seen at CeBIT. It features two DDR SDRAM memory channels, and supports Intel's future P4 processors with a 133MHz FSB clock (FSB533)."</i>
Hmm ... SiS using nVidia's technique used on the nForce Mobo, now in conjunction with a processor that could actually use the extra bandwidth? As stated in previous threads, the AXP doesn't benefit [more than 10%] of the TwinBank memory architecture, since it's FSB is limited to 64 bit @ 133 DDR = 2.1 GB/sec, which equals a single channel PC2100 DDR-RAM module's bandwidth. The double bandwidth available on the nForce was only useful for the integrated GPU, and maybe for DMA-accesses to the RAM, or AGP-texturing for an 'external' graphics card.
But now, using that very same bandwidth with a processor that has a 64 bit, 100 MHz (and future models, which will be supported according to the quote above, 133 MHz) QDR FSB, implying a 3.2 (or 4.2) GB/sec bandwidth, could lead to FENOMENAL performance improvements in comparison to nowadays available single channel DDR-solutions for the P4, I guess. Would this mean the end of RAMBUS memory, or will they be used in quad-banked configurations in the future (as they will be in Xeon MP-configurations)? Although ... I somewhere read that RAMBUS would be evoving to 32-bit-wide memory modules instead of 16-bit. Let's go and look some things up. I'll be back in a moment ...
Bikeman
<i>Then again, that's just my opinion</i>
<i>"SiS's Pentium 4 chipset SiS655 was also first to be seen at CeBIT. It features two DDR SDRAM memory channels, and supports Intel's future P4 processors with a 133MHz FSB clock (FSB533)."</i>
Hmm ... SiS using nVidia's technique used on the nForce Mobo, now in conjunction with a processor that could actually use the extra bandwidth? As stated in previous threads, the AXP doesn't benefit [more than 10%] of the TwinBank memory architecture, since it's FSB is limited to 64 bit @ 133 DDR = 2.1 GB/sec, which equals a single channel PC2100 DDR-RAM module's bandwidth. The double bandwidth available on the nForce was only useful for the integrated GPU, and maybe for DMA-accesses to the RAM, or AGP-texturing for an 'external' graphics card.
But now, using that very same bandwidth with a processor that has a 64 bit, 100 MHz (and future models, which will be supported according to the quote above, 133 MHz) QDR FSB, implying a 3.2 (or 4.2) GB/sec bandwidth, could lead to FENOMENAL performance improvements in comparison to nowadays available single channel DDR-solutions for the P4, I guess. Would this mean the end of RAMBUS memory, or will they be used in quad-banked configurations in the future (as they will be in Xeon MP-configurations)? Although ... I somewhere read that RAMBUS would be evoving to 32-bit-wide memory modules instead of 16-bit. Let's go and look some things up. I'll be back in a moment ...
Bikeman
<i>Then again, that's just my opinion</i>
) I think SiS is going to kick ass, if they will be able to implement what they plan in an efficient way (what they proved capable of with their recent 645DX). Intel is working on dual channel DDR-Ram, but I think they target only the high-end market, with prices according to it. RDRAM still has it's potential, but in pure bandwidth they [i.e. PC 1066] will be matched by dual PC 2100 and considering the high latencies encountered in a RDRAM-system ... But of course, who sais that 655 will be targeted at the low- to mid-end market we all belong to ...
Facebook
Twitter
Instagram