In this review, the A7N8X was configured with DDR 333 and DDR 400. The 400 proved to be slightly slower, most of the time. I'm curious to know if the CPU multiplier was changed so that the FSB and DDR speeds would be synchronized at 200Mhz, or if they ran async at 200/166. Also, if async, could someone speculate the results of a sync scenario?
Well, the K6-2 (along with other CPU's of the time) could be ran at a lower bus speed, but they ramped it up higher on the different boards, ranging form 66Mhz, 75Mhz, 83Mhz, and eventually 100Mhz stuck for a while. The clock generators though of the time, only were able to do 1 through 5 I believe, with 2 defaulting to 6 in some cases. The AXP is much more sensitive to FSB increases/decreases, which also will greatly affect the heat output and energy requirements
Instead of Rdram, why not just merge 4 Sdram channels...