Data to demonstrate Moore's Law

[poohbear90]

Hi everyone.

I'm working on a little project for school on the history of computing hardware. I've chosen to create a graph demonstrating Moore's Law. Whilst there are many graphs out there, I'm struggling to find raw data of MFLOPS, calculations per second, or transistor count of past and present microprocessors.

If anyone could point me towards some sources with relevant tables I would greatly appreciate it

 

[ubercake]

There's one on wikipedia:
http://en.wikipedia.org/wiki/Moore%27s_law

It doesn't help with the raw data though. Here's some info:
http://crab.rutgers.edu/~sundares/MIS334Sec40.Sp08/protected/notes/hw/moores.xls

This ends at 2004, but may help you get somewhere?

 

[jankyscoes]

CPU comparison guide: http://www.techarp.com/showarticle.aspx?artno=337&pgno=0

Benchmark list: http://www.notebookcheck.net/Mobile-Processors-Benchmarklist.2436.0.html

 

[Pinhedd]

A couple of links have already been posted here, but I'll provide a bit more insight.

Moore's Law isn't so much a law as it is a an observation that turned into an industry wide roadmap used by all the major chip manufacturers across all ASIC streams. In simpler terms, it's not something that just happens on its own, the entire industry works to make it happen and any period that meets the expectations set out by the law is considered a fairly good period.

In general, the industry hasn't kept up with Moore's law "exactly", but usually doubles some important metric every 18 to 24 months. There's always a bit of slack and in recent history that margin of slack has been widening.

The most cited metric for Moore's Law is transistor density and there's some empirical basis for this. The semiconductor node size roadmap is set out such that each new node size (65nm -> 45nm -> 32 nm -> 22nm and so on) cuts the surface area of a transistor approximately in half. The surface area of a transistor on a 45nm process is approximately half that of a transistor on a 65nm process (45 squared is about half that of 65 squared). Intel's roadmap introduces a new node approximately every 24 months, and a new architecture every 24 months but on the opposite year. Surprise surprise, Gordon Moore is the co-founder of Intel.

Halving the surface area allows approximately twice as many transistors to fit in the same physical package area, but also becomes increasingly more difficult to do. Intel, and its major competitors (IBM, TSMC, Global Foundaries, Samsung) have to constantly come up with new ways to make smaller node sizes work. As soon as they run out of ideas, or have to delay a new process, Moore's Law will stall out.

 

[poohbear90]

There's one on wikipedia:
http://en.wikipedia.org/wiki/Moore%27s_law

It doesn't help with the raw data though. Here's some info:
http://crab.rutgers.edu/~sundares/MIS334Sec40.Sp08/protected/notes/hw/moores.xls

This ends at 2004, but may help you get somewhere?

Thanks, the second link is good. I could use a few more data points, but it is certainly a good start

 

[poohbear90]

A couple of links have already been posted here, but I'll provide a bit more insight.

Moore's Law isn't so much a law as it is a an observation that turned into an industry wide roadmap used by all the major chip manufacturers across all ASIC streams. In simpler terms, it's not something that just happens on its own, the entire industry works to make it happen and any period that meets the expectations set out by the law is considered a fairly good period.

In general, the industry hasn't kept up with Moore's law "exactly", but usually doubles some important metric every 18 to 24 months. There's always a bit of slack and in recent history that margin of slack has been widening.

The most cited metric for Moore's Law is transistor density and there's some empirical basis for this. The semiconductor node size roadmap is set out such that each new node size (65nm -> 45nm -> 32 nm -> 22nm and so on) cuts the surface area of a transistor approximately in half. The surface area of a transistor on a 45nm process is approximately half that of a transistor on a 65nm process (45 squared is about half that of 65 squared). Intel's roadmap introduces a new node approximately every 24 months, and a new architecture every 24 months but on the opposite year. Surprise surprise, Gordon Moore is the co-founder of Intel.

Halving the surface area allows approximately twice as many transistors to fit in the same physical package area, but also becomes increasingly more difficult to do. Intel, and its major competitors (IBM, TSMC, Global Foundaries, Samsung) have to constantly come up with new ways to make smaller node sizes work. As soon as they run out of ideas, or have to delay a new process, Moore's Law will stall out.

Thanks for taking the time to respond. Unfortunately it is only a small project and I think they want to see are a few pretty graphs, but what you say is very interesting. I'll be sure to look into it. I read an interesting article elsewhere that argues that Moore's law (or variations of it) are useful for predicting rate of improvement of many other unrelated technologies.