RAM CAS Latency Vs CL Number

[peronto86]

Does anyone know the difference between CL and CAS Latency? For example, I have a 16GB PC3L-12800R-11-11-N1 ECC Server Ram, which is a CL11 according to the -11 in the number I've just given as an example and with a CAS Latency of 7 according to my RamCheck LX. So what exactly is the difference between CAS Latency (7) and CL (11)?

 

[brispuss]

CAS Latency = CL. CL is another way of writing CAS Latency.

The module label indicates a CAS Latency of 11 at its' rated bandwidth of 12800 MB/s = 1600 MHz operating frequency.

If RAMCheck LX indicates CAS Latency of 7 for this module, then either -

RAMCheck LX is in error and misreporting data, or

the module IS rated for CAS Latency of 7 at a lower frequency/bandwidth, or

the module has been mislabelled

 

[peronto86]

CAS Latency = CL. CL is another way of writing CAS Latency.

The module label indicates a CAS Latency of 11 at its' rated bandwidth of 12800 MB/s = 1600 MHz operating frequency.

If RAMCheck LX indicates CAS Latency of 7 for this module, then either -

RAMCheck LX is in error and misreporting data, or

the module IS rated for CAS Latency of 7 at a lower frequency/bandwidth, or

the module has been mislabelled

Our company has started an electronics resale trial and I've tested hundreds of RAM, but we are only just now selling to end users. Because I have so many, I can rule out that the module has been mislabeled as I am having this issue with multible different RAM models. I know the model I used in my example has a CAS Latency of 11 because it is being sold by other companies under the specification CL11. This means the issue is with RAMCheck LX. Is it possible the RAMCheck LX is testing at a CAS Latency below the RAM module's capabilities?? See "ARRAY TEST @CL7->" below in the readout. And thank you for your response.

BASIC TEST:
DDR3 DETECTED-REG
STRUCTURE TEST ->
RANK BITS DETECTED:
RANK 1:
CB DQ63-32 DQ31-0
FF FFFFFFFF FFFFFFFF
RANK 2:
CB DQ63-32 DQ31-0
FF FFFFFFFF FFFFFFFF
CONNECTOR WIRING-OK
MODULE`s SPD ID:
03 s/n=2416248966
SPD TS MFG ID:00B3
TEMPERATURE:22.50 C
DATA WIRING - PASS
DQS WIRING - PASS
ADD. WIRING - PASS
TEST AT SSTL 1.35V
SIZE: 2Gx72=16GB
CHIP SIZE: 8x128Mx4
=1Gx4
16 ROW/11 COL ADDR.
REFRESH:AUTO
RANKS: 2
-S:0+1
DQS:17..0
SPD=JEDEC
DDR3 240P DIMM
TEST TABLE #28
CODE=1274
TYPE: REGISTERED
ECC=Y
CLOCKS:1 CK0 PLL
BL TEST=4,8 - OK
SPD=1600MHz
SPD=PC3-12800
ARRAY TEST @CL7->
ARRAY TEST - OK
BT RETESTS: 0
TEMPERATURE:42.50 C
SPEED TEST RESULT:
TEST=PC3-12800
FINAL SPEED:1066MHz
BASIC TEST OK
TIME: 03:00.3
EXTENSIVE TEST:
USER INTERRUPT AT:
SPEED: 1066MHz
TIME: 00:33.8

 

[brispuss]

It is not known how RAMCheck LX carries out its testing procedures, but with some thought it appears that this is what is happening.

But first, memory behaves according to this formula: CAS Latency ÷ Frequency ~ Constant.

To calculate frequency at different CAS Latencies, the above formula becomes: CAS Latency ÷ Constant ~ Frequency

So for memory rated at bandwidth of 12800 MB/s = frequency of 1600 MHz and at a CAS Latency of 11 at that frequency, we have for the Constant:

11 ÷ 1600 ~ 0.006875 = Constant

So for CAS Latency of 7, the memory MUST run at a frequency of, CAS Latency ÷ Constant = 7 ÷ 0.006875 ~ 1018 MHz or around 1066 MHz ~ bandwidth of 8500 MB/s.

From the RAMCheck LX output above and from the above calculations, it appears that RAMCheck LX may be running the "Array Test" at the lowest CAS Latency the memory supports, and in this case at CAS Latency of 7. And at this CAS Latency of 7 the memory frequency HAS to be about 1066 MHz (~8500 MB/s) to satisfy the above formula. It is impossible to run memory at (much) higher frequency at this Latency value of 7.

The RAMCheck LX output appears to be slightly confusing and can lead to misinterpretation of results, especially as it seems to imply that the Array Test @ CAS Latency 7 is associated with the bandwidth of PC3-12800 (= 1600 MHz), but in fact this is impossible.

Assuming RAMCheck LX is functioning correctly, it seems to report the memory maximum bandwidth (PC3-12800) that the memory is capable of. It runs Array Tests at memory lowest CAS Latency rating (CL 7 in this case) which corresponds to a lower bandwidth of PC3-8500 = 1066 MHz.

Hope this clarifies things?

 

[peronto86]

It is not known how RAMCheck LX carries out its testing procedures, but with some thought it appears that this is what is happening.

But first, memory behaves according to this formula: CAS Latency ÷ Frequency ~ Constant.

To calculate frequency at different CAS Latencies, the above formula becomes: CAS Latency ÷ Constant ~ Frequency

So for memory rated at bandwidth of 12800 MB/s = frequency of 1600 MHz and at a CAS Latency of 11 at that frequency, we have for the Constant:

11 ÷ 1600 ~ 0.006875 = Constant

So for CAS Latency of 7, the memory MUST run at a frequency of, CAS Latency ÷ Constant = 7 ÷ 0.006875 ~ 1018 MHz or around 1066 MHz ~ bandwidth of 8500 MB/s.

From the RAMCheck LX output above and from the above calculations, it appears that RAMCheck LX may be running the "Array Test" at the lowest CAS Latency the memory supports, and in this case at CAS Latency of 7. And at this CAS Latency of 7 the memory frequency HAS to be about 1066 MHz (~8500 MB/s) to satisfy the above formula. It is impossible to run memory at (much) higher frequency at this Latency value of 7.

The RAMCheck LX output appears to be slightly confusing and can lead to misinterpretation of results, especially as it seems to imply that the Array Test @ CAS Latency 7 is associated with the bandwidth of PC3-12800 (= 1600 MHz), but in fact this is impossible.

Assuming RAMCheck LX is functioning correctly, it seems to report the memory maximum bandwidth (PC3-12800) that the memory is capable of. It runs Array Tests at memory lowest CAS Latency rating (CL 7 in this case) which corresponds to a lower bandwidth of PC3-8500 = 1066 MHz.

Hope this clarifies things?

Thank you very much. Your response was clear and informative. I think I may contact RAMCheck directly to see if they can confirm this theory. It seems strange to me that the machine would run an Array Test at memory lowest CAS Latency rating, but perhaps they have their reasons. Thanks again.

 

[brispuss]

You are welcome!

 

[Pinhedd]

It is not known how RAMCheck LX carries out its testing procedures, but with some thought it appears that this is what is happening.

But first, memory behaves according to this formula: CAS Latency ÷ Frequency ~ Constant.

To calculate frequency at different CAS Latencies, the above formula becomes: CAS Latency ÷ Constant ~ Frequency

So for memory rated at bandwidth of 12800 MB/s = frequency of 1600 MHz and at a CAS Latency of 11 at that frequency, we have for the Constant:

11 ÷ 1600 ~ 0.006875 = Constant

So for CAS Latency of 7, the memory MUST run at a frequency of, CAS Latency ÷ Constant = 7 ÷ 0.006875 ~ 1018 MHz or around 1066 MHz ~ bandwidth of 8500 MB/s.

From the RAMCheck LX output above and from the above calculations, it appears that RAMCheck LX may be running the "Array Test" at the lowest CAS Latency the memory supports, and in this case at CAS Latency of 7. And at this CAS Latency of 7 the memory frequency HAS to be about 1066 MHz (~8500 MB/s) to satisfy the above formula. It is impossible to run memory at (much) higher frequency at this Latency value of 7.

The RAMCheck LX output appears to be slightly confusing and can lead to misinterpretation of results, especially as it seems to imply that the Array Test @ CAS Latency 7 is associated with the bandwidth of PC3-12800 (= 1600 MHz), but in fact this is impossible.

Assuming RAMCheck LX is functioning correctly, it seems to report the memory maximum bandwidth (PC3-12800) that the memory is capable of. It runs Array Tests at memory lowest CAS Latency rating (CL 7 in this case) which corresponds to a lower bandwidth of PC3-8500 = 1066 MHz.

Hope this clarifies things?

Thank you very much. Your response was clear and informative. I think I may contact RAMCheck directly to see if they can confirm this theory. It seems strange to me that the machine would run an Array Test at memory lowest CAS Latency rating, but perhaps they have their reasons. Thanks again.

While his response is "clear", it is also nonsense.

Each DIMM is equipped with a small EEPROM called a Serial Presence Detect. The SPD contains a number of manufacturer specified parameters which can be used to calculate a set of JEDEC standard compliant configuration profiles. Memory controllers read this information and use it to configure the controller to the most desirable performance settings. When a compliant memory controller uses a compliant SPD to configure a compliant DIMM, interoperability is maximized.

The bulk of the information in the SPD originates from the DRAM manufacturer (Samsung, Hynix, Micron) rather than the DIMM manufacturer (Corsair, Mushkin, G.Skill, etc...). At each particular speed bin, the DRAM manufacturer specifies a minimum internal-read-to-first-data delay (tAA.min) which is the real time analogue of tCAS.

For example, the Samsung K4B4G0446Q is a very common 4 gigabit DRAM chip that specifies that is available in two speed grades (DDR3-1600 and DDR3-1866). Both chips are guaranteed to be backwards compatible with DDR3-800, DDR3-1066, and DDR3-1333. The DDR3-1866 speed grade is backwards compatible with the DDR3-1600 speed grade as well. However, the DDR3-1600 speed grade is not guaranteed to be forwards compatible with DDR3-1866.

Samsung specifies the minimum tAA for the DDR3-1600 speed grade as 13.75 nanoseconds. DDR3-800 has a clock frequency of 800Mhz which has a period of 1.25 nanoseconds. The specified tCL.min/tRCD.min/tRP.min for that chip is 11 and 11*1.25 nanoseconds = 13.75 nanoseconds.

If the vendor intends the chip to be used on a DIMM which is backwards compatible with the DDR3-1066 speed grade, the vendor must do at least two things to the SPD. First, they must enable compatibility with tCL 7 in addition to tCL 11, and they must lower tCL.min/tRCD.min/tRP.min to 13.125 nanoseconds.

tCL.max/tRCD.max/tRP.max are 20 nanoseconds regardless of speed grade.

What's happening with the tester is that it's most likely reading the SPD and using that information to gauge the configuration. In many cases the downstream DIMM vendors deliberately take the DRAM chips outside of specification for marketing purposes. They may overclock the chips or tighten the timings beyond those specified by the manufacturer. For example, DDR3-1600 CL 9 is common despite having a tCL.min of 10 nanoseconds which is outside of most manufacturer's specifications.

These vendor specific tweaks are not enabled automatically. They are stored separately on the SPD and will only be utilized if the user enables them either manually or by using Intel's XMP tuner.

What's happened in your case is that the RAMCHECK LX is working as intended:

DDR3 clock to 1333MHz, functional tests at 800MHz and 1066MHz, compatible with higher speed modules (with DDR3 adapter).

It`s running the test at DDR3-1066 CL 7 as specified in the RAMCHECK LX specifications.

 

[brispuss]

Largely disagree with this ^ comment!

SPD has nothing to do with memory performance. It just allows quick and convenient access to standard settings (voltage and timings) to enable memory to run (stably) at desired speeds according to the capability of said memory (which has been manufactured according to JEDEC standards).

The SPD can be manually overridden by the user, at anytime, in BIOS, and the user can then attempt any memory settings they desire. But whether those desired settings work or not is dependent on the characteristics/capability of the memory.

The equation: CAS Latency / Frequency ~ Constant, calculates the approximate effective latency of memory. The "~ Constant" actually means that it is approximately a constant value. Why approximate? Because of parasitic impedance and voltage variations this Constant value will vary a bit. But for constant voltage, the equation Constant will be more a constant value for differing frequencies for a specific memory module.

Have a look at the graph for True or Effective Latency here. It is noticed that the True/Effective Latency remains approximately constant for most of the memory frequency range.

However, it is possible (within limits) to run memory (at constant frequency) at slightly lower CAS Latency if the memory voltage is increased also. This tends to minimize the effect of parasitic impedance to a limited degree and so allows the memory to effectively run a bit faster.

But there are limits. It may be possible to get a reduction of typically one CAS Latency step/value by increasing memory voltage only, but no more.

For example, take memory rated at DDR3-1600, PC3-12800, CAL Latency 11, voltage 1.5V. It is possible to run this memory at a CAS Latency of 7, and at the same voltage 1.5V and at the same frequency of 1600 MHz? I bet you can't! Why? Because the memory is physically incapable of running (stably) with these settings.

 

[Pinhedd]

Largely disagree with this ^ comment!

Disagree all that you wish, what you wrote is still nonsense.

SPD has nothing to do with memory performance. It just allows quick and convenient access to standard settings (voltage and timings) to enable memory to run (stably) at desired speeds according to the capability of said memory (which has been manufactured according to JEDEC standards).

The SPD can be manually overridden by the user, at anytime, in BIOS, and the user can then attempt any memory settings they desire. But whether those desired settings work or not is dependent on the characteristics/capability of the memory.

RAMCheck LX is an external device. It is not a personal computer.

The equation: CAS Latency / Frequency ~ Constant, calculates the approximate effective latency of memory. The "~ Constant" actually means that it is approximately a constant value. Why approximate? Because of parasitic impedance and voltage variations this Constant value will vary a bit. But for constant voltage, the equation Constant will be more a constant value for differing frequencies for a specific memory module.

This is simply nonsense. It is entirely possible for SDRAM chips at a particular speed bin to be compatible with multiple latencies.
DDR3-1600G = 8-8-8
DDR3-1600H = 9-9-9
DDR3-1600J = 10-10-10
DDR3-1600K = 11-11-11

DDR3-1600G binned chips are by design backwards compatible with DDR3-1600H, DDR3-1600J, and DDR3-1600K. There is no guarantee that a DDR3-1600K chip will be forwards compatible with DDR3-1600H yet many are sold as such.

Have a look at the graph for True or Effective Latency here. It is noticed that the True/Effective Latency remains approximately constant for most of the memory frequency range.

Of course it is, the SDRAM IO bus primarily drives the front-end IO gating logic. The backend logic of SDRAM read operations is highly combinational and involves significant signal propagation. This is not a "constant" as you describe, it is a design parameter. Overvolting DDR3 can easily push tCAS to between 8 and 9 nanoseconds but this comes at the cost of stability, interoperability, and lifespan implications.

However, it is possible (within limits) to run memory (at constant frequency) at slightly lower CAS Latency if the memory voltage is increased also. This tends to minimize the effect of parasitic impedance to a limited degree and so allows the memory to effectively run a bit faster.

Parasitic impedance has nothing to do with it.

The nominal switching speed of a CMOS circuit with a fixed threshold voltage is directly proportional to the difference between the supply voltage and the reference voltage. Increasing the supply voltage shortens the 10-90 rise time and 90-10 fall time.

Increasing the memory supply voltage also increases the drive strength of the bit-line amplifiers as Vtt = Vdd / 2.

But there are limits. It may be possible to get a reduction of typically one CAS Latency step/value by increasing memory voltage only, but no more.

For example, take memory rated at DDR3-1600, PC3-12800, CAL Latency 11, voltage 1.5V. It is possible to run this memory at a CAS Latency of 7, and at the same voltage 1.5V and at the same frequency of 1600 MHz? I bet you can't! Why? Because the memory is physically incapable of running (stably) with these settings.

There are plenty of DDR3-1600 kits that are tested at CAS 7 at 1.5 volts.

Here's one

http://www.newegg.com/Product/Product.aspx?Item=N82E16820233683

 

[brispuss]

Thank you for your detailed response. But there is still I believe there is some misunderstanding on your part.

And I was not referring to RAMCheck LX device in my previous post.

True/effective latency is actually: 2000 x CAS Latency/memory frequency ~ constant, for that particular module with certain memory chips. The "Constant" value varies according to what memory chips have been used in the particular module.

This equation MUST define the effective latency for each specific module based on it's characteristics. Module characteristics are dependent on the memory chips used. Some memory chips allow low CAS Latency, other high CAS Latency.

Yes, there are modules @ DDR3-1600 with CAS Latencies as low as about 7, I believe, but that is entirely dependent on the grade/quality of the memory chips used.

So in the case of memory of DDR3-1600 with CAS Latency of 11, the grade of memory chips used must limit the CL to 11, so it will not be possible to run the module with lower CL (at same voltage). Yes?

 

[Pinhedd]

Thank you for your detailed response. But there is still I believe there is some misunderstanding on your part.

And I was not referring to RAMCheck LX device in my previous post.

True/effective latency is actually: 2000 x CAS Latency/memory frequency ~ constant, for that particular module with certain memory chips. The "Constant" value varies according to what memory chips have been used in the particular module.

This equation MUST define the effective latency for each specific module based on it's characteristics. Module characteristics are dependent on the memory chips used. Some memory chips allow low CAS Latency, other high CAS Latency.

Yes, there are modules @ DDR3-1600 with CAS Latencies as low as about 7, I believe, but that is entirely dependent on the grade/quality of the memory chips used.

So in the case of memory of DDR3-1600 with CAS Latency of 11, the grade of memory chips used must limit the CL to 11, so it will not be possible to run the module with lower CL (at same voltage). Yes?

The absolute lowest tCAS that can be programmed on any DDR3 SDRAM chip is 5 and the absolute highest tCAS that can be programmed on any DDR3 SDRAM chip is 14. These are design constraints that cannot be bypassed regardless of speed grade.

The DDR3 SDRAM chip requires at least one cycle to perform the combinational logic on the backend and serialize the 8 words for the read command into the IO logic. Then it requires 4 cycles (fixed) to transmit the data on the IO bus, with one transmission occurring every half cycle.

In practice, the back-end logic can only be performed in a single cycle at extremely low command clock frequencies (at or below DDR3-800, or 400Mhz), but the front-end transmission logic takes 4 cycles regardless of the configured data rate. At higher data rates, the bulk of the time is spent waiting for the backend.

There are two ways to speed this up:

1. Crank up the supply voltage

2. Hand pick the best chips and put them together

The JEDEC specifications are meant to maximize interoperability and stability, they pay little heed to performance. tCAS means little when employed in industrial and medical devices, but stability is very important.

There are only a small number of DDR3 SDRAM chips on the market.

Samsung has only two 4 gigabit DDR3 die designs that I know of (with minor stepping revisions of each), the K4B4G0446 which is a 4 gigabit chip with 4 IO pins, and the K4B4G0846 which is a 4 gigabit chip with 8 IO pins.

Hynix operates in the same way. They have 3 4 gigabit DDR3 die designs with minor stepping revisions of each. H5TC4G43 with 4 IO pins, H5TC4G83 with 8 IO pins, and H5TC4G63 with 16 IO pins.

Micron is the same as well. They have 3 4 gigabit DDR3 die designs. MT41K1G4RG with 4 IO pins, MT41K512M8RG with 8 IO pins, and MT41K256M16LY with 16 IO pins.

In general, each manufacturer makes each die available as a 1.5v DDR3 chip and a 1.35v DDR3L chip. Then, each chip is made available in 2-3 speed grades. Presently, DDR3-1600, DDR3-1866, and DDR3-2133 are available from manufacturers. Each is of course backwards compatible.

What this means is that all of the various DIMMs available on the consumer market are nearly identical underneath the heat spreader. Almost all 8 gigabyte unbuffered DIMMs will be constructed as two ranks of 4 gigabit 8-IO DDR3 SDRAM chips. This means that the selection of chips are limited to the K4B4G0846 from Samsung, the H5TC4G83 from Hynix, and the MT41K512M8RG from Micron.

Purchasing a tray of higher speed-grade chips may enable the DIMM manufacturer to squeeze a little bit of extra performance out of the resulting DIMM by virtue of the SDRAM manufacturer's testing process.

For example, the K4B4G0846Q (the latest stepping of Samsung's 4 gigabit 8-IO DDR3 die) is available in two speed grades. It is available as K4B4G0846Q-HCK0 (DDR3-1600 11-11-11), and K4B4G0846Q-HCMA (DDR3-1866 13-13-13).

An assortment of K4B4G0846Q-HCMA may, without overvolting, have an easier time running at a very tight non-standard profile such as DDR3-1600 7-8-7 than the K4B4G0846Q-HCK0. Neither Samsung, nor JEDEC, nor Intel make any guarantees when their products are used outside of the standards to which they are designed.

It is therefore very important to separate the theory, the standards, and the implementation from each other.