The History Of Intel CPUs (Archive)

[IInuyasha74]

From the 4004 in 1971 to Skylake in 2015, we look at the evolution of Intel's CPUs.

The History Of Intel CPUs : Read more

 

[adamovera]

Archived comments are found here: http://www.tomshardware.com/forum/id-3086382/history-intel-cpus.html

 

[uglyduckling81]

I'm not sure your summary of Kaby is accurate. It's more like you just copy, pasted from their advertising material.
It runs hotter if anything, though it's fair to say it runs the same. The only real change is their improvements in actual yield quality allowing them to release slightly higher clocks at stock.

 

[Nevering]

From what I've seen then Kabylake is no better than Skylake especially at gaming.

 

[razamatraz]

If Coffee Lake is going to be 14nm as well are we not getting a Tick-Tock-Tock-Tock cadence now? Cannon Lake is 10nm but is not releasing in the desktop or laptop CPU types, only in the embedded ultra low power. So we got proces with Broadwell, Architecture with Skylake, Optimize (debatable) with Kaby Lake and Optimize again with Coffee Lake?

 

[PUPPLESAN]

Tick | tock | KA-CHING. I don't blame Intel at all--they are running up against the basic structure of matter and meantime have to make money somehow--- but the second tock is a not exactly a great reason to rush-buy a new system. Left un-described is the unholy terror that settles-in the minds of Intel investors once circuit sizes drop below about 3-5 nano-meters. Unless quantum computing proves practical and possible, the "ticks" and "tocks" will begin to herald little more than infinitesimal performance gains. They kind of already do.

 

[stanljl]

Enjoyed the read thank you.

 

[genz]

@Pupplesan

Die shrinks aren't giving the performance boosts they used to and I highly suspect that Intel 10nm is more mobile than max-clock optimized (like ARM nodes) hence the worse top end performance (Process nodes have a power curve like cars). If Intel are smart they will be trying to get their mobile chip sales to scales where they can do their Extreme and Xeon chips on a less efficient, more higher clocking process node and stick everything from Atom and Core M to i7 Ks on 10nm. The price gap will be as wide as now, but then 2011 socket processors might finally see Intel really working on top end performance again.

 

[bit_user]

Some major technical errors and oversights are still not fixed from the previous version. My comments about the previous version are here: http://www.tomshardware.com/forum/id-3086382/history-intel-cpus.html#18111237

I've confirmed and copied the most significant of them below.

the 16-bit data bus and execution hardware allowed the 8086 to simultaneously work on two eight-bit instructions.

No. The 8086 was not a SIMD-capable CPU, nor any more superscalar than the 8088. Please fix it.

It'd be accurate to say that it could fetch twice as much data per bus cycle.

... the 8088 around the same time. This processor was based on the 8088, but it disabled half of the address bus, limiting it to eight-bit operations. As it still had access to up to 1MB of RAM and ran at higher frequencies

Half the data bus - not half the address bus. It was merely a performance-reduced version of the 8086, due to crippling the memory bus (as you point out). It was instruction-set-compatible with the 8086, however, and could execute all of the former's 16-bit instructions. It was in my first PC.

And no mention of 8087?

The 286 included the notable introduction of support for protected mode. The importance of this cannot be overstated. It set the groundwork for all modern operating systems: protecting different processes & the kernel from each other, and enabling support for virtual memory. Without memory protection, your PC would only be as reliable as the most buggy program you ran. And a bad program crash could even result in hard drive corruption.

To segment its product line-up with a more budget-friendly offering, Intel also introduced the 80386SL. This processor was almost identical to the 32-bit 80386, but was limited to 16-bit operations.

I think you mean 386SX. Maybe 386SL was a follow-on laptop chip... Anyway, again "limited to 16-bit operations" makes it sound like a 16-bit CPU. It wasn't - just had half the memory bus width, similar to what they did with the 8086 vs. 8088. It's not clear to readers that you're talking about memory bus operations, rather than instructions.

Intel also introduced the new LGA 775 interface that featured support for DDR2 memory and improved the quad-pumped FSB.

I had a socket-475 P4 Prescott with quad-pumped FSB. I think even some Northwoods had it.

The chipset for LGA 775 introduced PCIe support.

Prescott was also Intel's first 64-bit x86 processor, allowing it to access more RAM.

Prescott was rumored to have 64-bit support, but it was disabled. I actually wonder how much of its heat/performance problems came from all the baggage of 64-bit.

Pentium D was actually the first desktop Intel CPUs with x86-64 support enabled. Maybe a Prescott Xeon had it first... not sure.

 

[mitch074]

Quite a few errors...
The "nerfed" version of the 386DX was the 386SX - 16-bit data bus instead of 32-bit. This prevented the use of then-new 32-bit FPM DRAM, but allowed one to use pairs of 9-bit RAM sticks (instead of 4 identical 9-bit RAM sticks). The 386SL did exist, it was a 386SX with croutons: it added the HLT instruction that allowed the CPU to power down when not in use (instead of running a NOOP instruction). That, and the smaller data path making system connection smaller, were very useful for the then-growing laptop market.
Yes, I did put my hand on all 3 CPUs (I had a 386DX20, a friend owned a 386SX25, and I once took apart a magnificent laptop that had an AMD 386SL).
Other (MAJOR) error: the first Celeron to include L2 cache on-die was the Mendocino (of Celeron 300A fame), which was a P-II grade part. I had one, too - of course, running at 450MHz.

 

[bit_user]

I've now separated out my more minor points into another post. Again, most of these were originally mentioned in http://www.tomshardware.com/forum/id-3086382/history-intel-cpus.html#18111237

80186 was never really used in PCs, AFAIK. I think it was mostly used in control applications, for some reason. Would be interesting to know why.

I think the 486 was the first pipelined x86 CPU. The entry also could have mentioned the decoupling of the core & memory speeds. We had the whole DX2 series of chips, with half the memory bus frequency. I even had an AMD 486 DX4 100, with a 100 MHz core clock and 25 MHz memory. Around the time of 386/486, the transition from chip RAM to SIMMs also happened.

Pentium was Intel's first superscalar x86, meaning it could execute two instructions simultaneously. It was the first x86 CPU with support for multi-processor SMP, and dual-CPU Pentium mobo's weren't so uncommon. The PCI bus also appeared with the Pentium, but this was a chipset/mobo feature. If you don't count the Pentium MMX, I think the fastest Pentiums were just 200 MHz.

The Pentium II entry shows the board, but no mention is made of the "Slot 1" socket they used.

Pentium III introduced SSE: Intel's 128-bit vector instructions for floating-point. This is the first time they supported vector floating-point operations. Even for scalar arithmetic, it's much faster than x87 instructions.

Pentium 4 introduced SSE2, extending 128-bit vector support to integers.

Core was a separate CPU iteration than Core 2. It supported slightly different instructions than Core 2, and came about 1 year earlier. Intel confused the matter by using Duo vs. Solo to distinguish the number of CPU cores, and I don't recall any Core Duo's - only Core 2 Duo's. I don't consider Core 2's still viable, BTW. It's theoretically possible, but I pity any poor souls doing it.

Atom brought back Hyperthreading, BTW. That was supposed to compensate for lack of out-of-order, but the reality was that it didn't.

Nehalem was the first & only generation (so far) to have 3 memory channels, which was pretty bizarre. Also, PCIe was not on-die for at least some of the CPUs. It went over Quickpath to the chipset, which implemented the PCIe.

Sandybridge introduced AVX: 256-bit floating point vector instructions.

With Ivy Bridge, Intel switched from soldering desktop CPU's IHS to using heat sink compound. This, coupled with Ivy's smaller die size are common blamed for the Ivy's inferior overclockability.

Haswell introduced AVX2, extending AVX to support integers.

IMO, it's not worth mentioning SSE3, SSSE3, SSE4.1, SSE4.2, etc. because these were just tweaks on the existing capabilities, rather than the huge advancements represented by MMX, SSE, SSE2, AVX, and AVX2. AVX-512 is a little hard to fit in, because it still hasn't been launched in any mainstream products.

Silvermont also dropped hyperthreading.

Conspicuously absent: Itanium & IA64. This important piece of Intel's history tells a lot about how AMD was able to beat them to 64-bit support, on the desktop, and possibly even explains PAE. It might even explain why Intel continued to push x86 into low-power and mobile, in spite of the inherent advantages of a RISC ISA like ARM. Basically, every time Intel has ever tried to deviate from x86, they've gotten burned. I think they might've learned that lesson too well.

I can understand leaving out IA64 for a separate article, but then why are the other non-x86 ISA's included here?

 

[mitch074]

80186 was never really used in PCs, AFAIK.

It was used in a couple "PC-compatible" systems - but not much, as it didn't bring much to the table and the 286 was soon much more interesting than it.

I think the 486 was the first pipelined x86 CPU. The entry also could have mentioned the decoupling of the core & memory speeds.

Yeah, that.

I think the fastest Pentiums were just 200 MHz.

Yes, and it ran like a dog due to its 2.5x multiplicator which left its pipeline starved most of the time; the MMX included a couple more stages to its pipeline, which offset the problem.
A Pentium 133 overclocked to 2x83=166 MHz (which was an unofficial speed found on many 430TX-based motherboards of the times) scored the same as a P200.

The Pentium II entry shows the board, but no mention is made of the "Slot 1" socket they used.

It is (indirectly), when mentioned that the L2 cache ran at half-speed on a daughter board.

Core was a separate CPU iteration than Core 2. It supported slightly different instructions than Core 2, and came about 1 year earlier.

It was pretty much to prepare the market to a return of the P6 architecture to the desktop; it was a glorified Pentium-M.

I don't consider Core 2's still viable, BTW. It's theoretically possible, but I pity any poor souls doing it.

The Core 2 Quad if good for productivity work (I still have a few running at work). Forget about gaming or rendering with it, of course - powerhogs.

Haswell introduced AVX2, extending AVX to support integers.

Worth noting too, is that Haswell had 2 spins, the second being dubbed "refresh" with slightly higher clock speed but also a better heat spreader paste.

Conspicuously absent: Itanium & IA64.

Well, it was such an embarrassment... Imagine, Intel's been shouting that IA64 was the future of computing, they had HP selling off IA64-based servers left and right, they convinced Microsoft to compile Windows Server for IA-64... And nobody bought them. Even worse, as you said, AMD pulled AMD64 out of their hat, solving several flaws of the x86 on the way (doubling the registers was a boon for many a programmer).

With Intel trying to bury news sites with their paper Coffee Lake CPU launch, reminding readers of Intel's worst failure would look bad.

 

[Tom Griffin]

Pentium Pro first processor from Intel to do out of order execution. https://en.wikipedia.org/wiki/Pentium_Pro

 

[John Philips]

Who else ended up reading this overclocking article from1997? http://www.tomshardware.com/reviews/overclocking-guide,15-14.html

 

[Martell1977]

I understand that the major changes or families of Intel CPUs are here with some details but I am surprised that there was no mention of which generation got the honor of using thermal paste over solder, which has been a issue ever since. Other missteps are mentioned, why not this one?

 

[bit_user]

Conspicuously absent: Itanium & IA64.

Well, it was such an embarrassment...

In the context of the article, a number of other non-x86 (and mostly unsuccessful) ISAs were covered. I wonder why not either make two articles (one for x86-only; another for non-x86) or just include IA64 in this one.

It definitely helps people understand how AMD got the lead on 64-bit.

 

[bit_user]

I am surprised that there was no mention of which generation got the honor of using thermal paste over solder, which has been a issue ever since. Other missteps are mentioned, why not this one?

I mentioned that about Ivy Bridge, in my comments above. But, I wonder when did Intel first use solder beneath the IHS?

 

[IInuyasha74]

I understand that the major changes or families of Intel CPUs are here with some details but I am surprised that there was no mention of which generation got the honor of using thermal paste over solder, which has been a issue ever since. Other missteps are mentioned, why not this one?

This is just something that didn't make it into the article. Ivy Bridge is the first one in recent years to use TIM between the CPU and IHS instead of being soldered on. Intel has continued to do that since. It isn't the first one to experience this treatment though. Prior to Intel's Tualatin Pentium 3 CPUs, IHSs weren't common. That was the first consumer chip made by Intel to come with one, and it was glued on with TIM between the CPU and IHS, not soldered. Select models of the Pentium 4 had the IHS soldered, but not all of them. This appears to have been a transitional period for the company, as all Pentium D CPUs had the IHS soldered as well. All 1st Gen and 2nd Gen Core processors also had it soldered on.

I'm not sure about Core2Duo though. It may be interesting to know that AMD has been more consistent on this issue, and it has soldered the IHS down on every CPU since the days of the original Phenom.

 

[mitch074]

I mentioned that about Ivy Bridge, in my comments above. But, I wonder when did Intel first use solder beneath the IHS?

Probably with the Pentium 4, as it was the first to use a heat spreader directly over the chip - and also needing high energy dissipation (PPro and -MMX had a heat spreader too, but the chip itself wasn't soldered to the IHS - they were on the other side of the package).
Since delidding wasn't exactly a thing back in the day, records are spotty.

 

[takeshi7]

I mentioned that about Ivy Bridge, in my comments above. But, I wonder when did Intel first use solder beneath the IHS?

Probably with the Pentium 4, as it was the first to use a heat spreader directly over the chip - and also needing high energy dissipation (PPro and -MMX had a heat spreader too, but the chip itself wasn't soldered to the IHS - they were on the other side of the package).
Since delidding wasn't exactly a thing back in the day, records are spotty.

Actually the Pentium 3 Tualatin was the first Intel CPU to have a heatspreader that's designed like modern CPUs, but even older CPUs like the higher clocked 486 DX4 and Pentium had metal caps to dissipate heat. I've dissected a Pentium Pro and can confirm that Intel used a solder to bond the die to the metal cap back in 1995.

 

[takeshi7]

I think it's very interesting that every modern Intel CPU is a direct descendant of the P6 architecture that's over 20 years old. Just with refinements and features added every generation. So Netburst was really Intel's newest from-scratch x86 microarchitecture. So my Pentium D is from a newer microarchitecture than Coffee Lake.

 

[aldaia]

I think the 486 was the first pipelined x86 CPU.

Technically speaking, the first pipelined x86 was the 8086 itself. The 8086 architecture was divided into 2 parts or units:

• 
  ■ Bus Interface Unit(BIU)
  ■ Execution Unit(EU)

8086 had a instruction queue of 6 bytes. While EU was busy executing instructions, the BIU fetched other instructions from main memory into the instruction queue, making possible fetching and execution of instructions simultaneously. The BIU is programmed to fetch a new instruction whenever the queue has room for one (with the 8088) or two (with the 8086) additional bytes. Although limited, that is a 2-stage pipelined processor. 486 used a 5-stage pipeline. Some modern pipelined processors like ARM-M family have either 2 or 3 pipeline stages.

That may also explain why the article, erroneously, says "the 16-bit data bus and execution hardware allowed the 8086 to simultaneously work on two eight-bit instructions". That wording seems to imply 8086 was superscalar which is not true. But 8086 (and 8088 too) could overlap fetch and execute stages of 2 instructions.

 

[weberdarren97]

I like the short description for Skylake. Especially the part where it says that the platform changes are more important than the faster CPUs, because we all knew that Intel wasn't going to do any massive innovations until AMD caught them with their pants down.

 

[bit_user]

That may also explain why the article, erroneously, says "the 16-bit data bus and execution hardware allowed the 8086 to simultaneously work on two eight-bit instructions".

Please don't muddy the waters. That statement is wrong, as most people would interpret it, and needs to be fixed.

That wording seems to imply 8086 was superscalar which is not true.

Agreed.

 

[bit_user]

I think it's very interesting that every modern Intel CPU is a direct descendant of the P6 architecture that's over 20 years old.

No, only the Pentium II should've been a direct descendant.

Just with refinements and features added every generation.

Perhaps if you consider modern birds to be dinosaurs with refinements and features added, then yes. But if you examine the actual hardware designs, you'd probably be hard pressed to find any part of the implementation that's still recognizable from the Pentium Pro. Conceptual similarities are probably all that's left.