Crashman :
...It's clear from this review alone that DDR4-3733 overclocked to 4000 beats DDR4-3866 overclocked to 4000, beats DDR4-4600 overclocked to 4000, and the easiest explanation is that lower-frequency performance RAM is programed to take advantage of the tighter advanced timings that are stable at that lower rated frequency. There's obviously some "slack" in the timings of each kit to assure its stability across less-stable platforms, and we're evidently using up that slack when we overclock.
Crucial did a pretty good write-up on speed (frequency) vs latency. In the past, I've always choose the highest clocked memory that was still within specification, and not yet classified as OC-ed . Meaning, when it came to cost, I've biased the purchased decision based on latency. Turns out I was kinda wrong. Apparently it's not just latency, it's about "true latency" after factoring in the forumla of clock cycle time (ns) x clock cycles (CL).
http://www.crucial.com/usa/en/memory-performance-speed-latency
Of course, that goes back to what you said of OCing lower latency modules to higher frequencies. But at some point, sacrificing stability for performance isn't a trade off worth having IMHO. Google already did large scale field study on DRAM errors, and surprisingly they were higher than initially thought. And mind you, that's non OCed memory!
"We find that DRAM error behavior in the field differs in many key aspects from commonly held assumptions. For example, we observe DRAM error rates that are orders of magnitude higher than previously reported, with 25,000 to 70,000 errors per billion device hours per Mbit and more than 8% of DIMMs affected by errors per year. We provide strong evidence that memory errors are dominated by hard errors, rather than soft errors, which previous work suspects to be the dominant error mode. We find that temperature, known to strongly impact DIMM error rates in lab conditions, has a surprisingly small effect on error beha vior in the field, when taking all other factors into account. Finally, unlike commonly feared, we don’t observe any indication that newer generations of DIMMs have worse error behavior."-Google
https://ai.google/research/pubs/pub35162
Now consider that the study is about 10 years old already in addition to higher frequencies and denser transistor counts, and I can only imagine bit-flip error stats getting worse. I'd love to see a followup to that study regardless.
My only point is that everyone wants to put emphasis on speed while sacrificing stability. At some point, I would not be surprised in fact if the entire industry makes ECC somewhat the defacto standard going forward for consumer products. And in doing so, I'm sure there will be an outcry given the small performance hit that it would have in the OC-ing community.
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