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Started by sharanbr | | 16 answers
Xeon Architecture or block diagram
Hello All,

Can anyone give me pointers as to where I can find some good block diagram or Architecture for Xeon processor. Mainly I am a little confused with the number of root complex ports in the system (not just processor but full system), how these root complex ports are used, interface from processor to chipset, chipset to south bridge, concept of PCH etc.

If someone can help me with some pointers, I would be very thankful
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a c 198 à CPUs
October 17, 2014 10:54:43 AM

sharanbr said:
Hello All,

Sorry to open this thread once again. A few more questions ...

Is there a difference between IO controller hub and platform controller hub.
BTW, what exactly is the purpoe of IO Hub?


South Bridge, IO Controller Hub, and Platform Controller Hub are three different names for the same thing. PCH is a newer term that has come into use now that the North Bridge has been more or less completely integrated into the CPU package.
October 17, 2014 10:03:41 AM

Hello All,

Sorry to open this thread once again. A few more questions ...

Is there a difference between IO controller hub and platform controller hub.
BTW, what exactly is the purpoe of IO Hub?
a c 198 à CPUs
October 6, 2014 1:19:00 AM

sharanbr said:
Dear AdmiralDonut,

Thank you very much. This is very comprehensive.

Dear AdmiralDonut, Pinhedd,

I have a few questions mainly to clear out some basic doubts I have regarding uses of various interfaces,

1. PCIe Gen3 ports avilable on processor - can you let me know a couple of examples the type of application this is used for?

Somewhere I remember seeing graphics processor but is it not that now the processors integrate graphics IP within CPU itself?

2. Are both DMI and FDI used simultaneously by the PCH chipset?
This is the way it is shown in one of the figures.


1. On desktops, these are most commonly used for discrete graphics cards. On servers they are used for storage controllers, storage devices, coprocessors, etc... Anything that can be attached to the PCIe 3.0 lanes on the CPU can also be attached to the PCIe 2.0 lanes on the PCH. The benefit of attaching them to the CPU is a shorter path to the system memory which is helpful for bandwidth hungry devices such as graphics cards.

2. If the CPU has an IGP, the chipset is connected via both DMI and FDI at the same time. The DMI connection is a proprietary implementation of PCIe, and FDI is a proprietary implementation of DisplayPort.
October 6, 2014 12:50:12 AM

Dear AdmiralDonut,

Thank you very much. This is very comprehensive.

Dear AdmiralDonut, Pinhedd,

I have a few questions mainly to clear out some basic doubts I have regarding uses of various interfaces,

1. PCIe Gen3 ports avilable on processor - can you let me know a couple of examples the type of application this is used for?

Somewhere I remember seeing graphics processor but is it not that now the processors integrate graphics IP within CPU itself?

2. Are both DMI and FDI used simultaneously by the PCH chipset?
This is the way it is shown in one of the figures.
October 3, 2014 2:06:16 AM

Thank you very much, AdmiralDonut ...
a c 198 à CPUs
October 2, 2014 11:24:45 AM

sharanbr said:
Dear pinhedd, thank you very much. I can't describe how much the response helped me ...


You're most welcome
a b à CPUs
October 2, 2014 10:18:43 AM

sharanbr said:
Hello All,

Can anyone give me pointers as to where I can find some good block diagram or Architecture for Xeon processor. Mainly I am a little confused with the number of root complex ports in the system (not just processor but full system), how these root complex ports are used, interface from processor to chipset, chipset to south bridge, concept of PCH etc.

If someone can help me with some pointers, I would be very thankful


Have you seen this? http://www.intel.com/content/www/us/en/intelligent-syst...

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