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While I love automation, people need jobs so we need to strike a balance between the two.

Semper Fi Carry^H^H^H^H^H Linux on :-D

The real story behind AMD and Intel production methods is in the numbers from when they were fighting it out in flash. Flash is pure commodity. No premiums regardless of how high performance the modules are. Granted AMD had mirrorbit and Intel had their MCP's, Intel was losing on the order of $200million just to eek $100million in losses out of Spansion at the peak of the struggle. That killed AMD's bottom line cheaply for Intel and undoubtedly hurt AMD's momentum, but it also demonstrated that Intel had a hard time bringing on the pain in head to head production. Neither company was using cutting edge production to build flash. It came down to their ability to utilize their fabrication equipment. AMD won. Now that Intel is out of the AMD sinking business, Spansion has been performing quite well. Flash is where I drew my conclusion. The rest is all honestly just me justifying that position.

One thing I need to point out, Intel isn't part of the Sematech group, so they don't show up on that graph. Not that I, well maybe I would have let you imply it

Here's my (slightly stale) table to point to on Intel's fab standing:
http://www.intel.com/pressroom/kit [...] glance.pdf
One thing worth mentioning is that AMD took 21.4% unit market share with one 200mm FAB.

Interesting point. But CE is kind of a cultural thing, don't you think? My understanding is that it was an evolved-to status. If AMD has no similar experiences, it seems that they would have to jump as least some of the hurdles themselves, even if they have much specific info about the CE process.

AMD's fabs are all in one location. Copy exact sought to elminate variables from the production process. One fine example was when the Arizona fab wasn't up to expectations. Engineers noticed that the Oregon air had to be dehumidified, whereas Arizona is baked to begin with. The dehumidification process was also removing some other components that turned out to be hurint production at Arizona, so Intel installed humidifiers and dehumidifiers to recreate the same conditions as exactly as possible. I've heard other stories such as using the same kind of gloves on the production line and such. I'm sure the rest has to do with configuring the fab equipment itself, but you get the idea.

AMD just doesn't face those challenges. Their two fabs are side by side. The upgraded fab 30 will be fab 38. Still side by side. I don't see AMD ever moving to copy exact. In any case, APM did serve them well when maintaining flash production in Texas and CPU production in Dresden.

I like APM because it reminds me of EDO, Execution Directed Optimization in GCC 4.0. You run a test binary with profiling code inserted to find the most influential code spots and then optimize the hell out of them. It also reminds me of Acovea's compiler solution. There are simply too many variables to use production and brute force analysis to find an optimal solution to complex relationships. Everyone can use feedback to optimize their fab controls, but it seems AMD is ahead of the game when it comes to using statistical analysis to find the most influential variables and how they relate to other steps in the production process.

The last presentation I saw on Intel's production technique talked up how Craig Barret discovered that making some units in the fab wait for others would increase overal utilization, in contrast with the layman's approach, going from unit to unit to unit as soon as the dough rises. It's smart, but it just didn't blow me away.

SexBomb, if it's you I'm glad to have you here once again.

This is too funny.

Sure, I follow all that. CE also extends to Intel's suppliers and that's how I got introduced to it. Any changes to a supplied product had to go through a rigid qualification procedure. One advantage from Intel's perspective was that a supplier had to pony up some of their own R&D bucks to make a change to their own production. This made the supplier think twice about whether or not they REALLY needed to make a change. Any company will have individuals that try to make their mark by attaching their name to change. Thus it's common to have change that is brought about by individual goals (read: greed, ego) rather than by a true technology need or business advantage.

Its good to know that 9-inch has a special little friend

I'm 20. I go to the University of Oklahoma. I have been investing for eight years (six under the Oklahoma UTMA). And Goddamnit, I can dance:


Does anyone know anything about Rev-G or have enough technical knowledge to comment on the die pic? Any information on whether or not the first 65nm parts will be rev-g would also be appreciated.

Granted the 65nm pic doesn't say anything about being Rev-G, I'll still make this inference:
It's different than Rev-F
It's not K-8l, Rev-H
There is a Rev-G
The pic is somewhere in between Rev-H and Rev-F, so I'll call it Rev-G.

There are prominant layout changes between the instruction cache on the 65nm cad shot and the Rev-F. There is what looks like an extra bit of SRAMS sandwiched between the L2 cache and L1 data cache. There is an extra square "mojigger" at the same location as and identical to the three square "mojiggers" in the instruction fetching area. The SRAM looking "thingamajigs" that occupy the area obove the L1 data cache on the Rev-F have been rearranged, cut into two halves, and positioned right next to the L1 data cache. I believe these to be an exta complex decoder, an out of order L2 load buffer, and maybe a read/write buffer modified for out of order reads to main memory, respectively. Can anyone with some VLSI experience or any experience potentially more enlightening that mine in MIPS design (irrelevant by now) please try to comment on the likelyhood of these changes?

I still have been unable to determine whether or not any of the first 65nm devices will be Rev-G. I know it takes time for a device to tape out, but from what I can tell, AMD is pulling PR punches in order to maximize ROI on the current generation of chips and to postpone depreciation on 65nm production tools in Fab 36 until they are needed for revenue production.

Just saw this...internet source, but It's better than nobody:
http://www.reghardware.co.uk/2006/ [...] nm_dec_06/

Clockspeeds are the same it seems. I had heard some noise about Brisbane being Rev-G, but the clocks are the same as today's 939-pin parts.

http://www.xbitlabs.com/news/cpu/d [...] 53242.html

My Chinese is still just a dream, but if you must:
http://www.hkepc.com/bbs/news.php?tid=599540

Close enough to answering my question. I'm going to be a bit skiddish on AMD unless Intel cludges a bit, and real reviews show a slightly less glamorous story than the Intel prepaired machines. Might short the hell out of them if Q3 numbers show signs of marketshare erosion. Still, I'm definitely into AMD and Rackable whenever K-8l ramps. Seems it will be totally superior to anything Intel can field until Nehelem at earliest. FSB is like a foundation of quicksand.

I am falling in love with Dallas and Houston. Tokyo 1 in Dallas has all you can eat sushi bar. Bamboo leaf is best Tai restaraunt...best restaraunt I've ever eaten at. Better clubs. Karaoke bars open until a reasonable hour (6am). Better beer. Dave and Busters, Fuddruckers, Julians, Jack in the Box...it goes on and on. Oklahoma is slowly killing me every time I get back, but luckily I'm headed for a study abroad in Kyoto next year.

I found a bigger pic on a german site. Wish I could understand the rest.



http://tweakers.net/nieuws/41961/G [...] on-64.html

Edited:
More German goodness...how is I've been missing this stuff?


http://www.meisterkuehler.de/forum [...] -core.html

Yep, not just better FSB and cache and hopefully improve memory controllers as well. No doubt it would be a great archeticture and granted the Conroe's performance this chip will undergo all kinds of tweakings and improvements to counter it.

And K8's just a K7 with an onboard memory controller...right... Let him call it what he well. I still see changes.


edit: quote for context
edit2: (lameness)--

And who said that?

Hey Action Man what happened to the one-eyed action man?

He got too much man action, and his other eye got poked out.

As I said, they all give data to Sematech and Sematech tells them whether or not to fire all their production engineers. Each company gets a letter. They get the graph. They know their letter. They do not know anyone else's. Read more on the benchmark.

AMD is the best:
http://epscontest2.home.comcast.ne [...] lide27.JPG

AMD ramp times getting better and better. 65nm ramp should likewise take very little time, and they've had 65nm SRAM's working for over six months:
http://epscontest2.home.comcast.ne [...] ide108.jpg

AMD ramped fab 30 way beyond it's original 15k (wafer starts per month) capactiy and was running at 30k by Q1, increasing from 150% they were already running at:
http://epscontest2.home.comcast.ne [...] lide33.JPG

AMD moves wafers through the fab generally at the fastest rate in the industry:
http://epscontest2.home.comcast.ne [...] ide110.jpg

Over 400 things in APM that Intel does not do:
http://epscontest2.home.comcast.ne [...] ide113.jpg

Intel pays the most for AMAT's most advanced parts. This is why they lead process shrinks (geometry only). They are behind the curve in virtually everything else though. They do not do dual-strees liner, SOI, and now they are even balking at the immersion lithography technology and once more proving they're arrogant beyond comprehension. Not invented here. Intel has a history of getting horrible results out of their process shrinks and taking absolutely forever to tweak their processes.

The reason you never saw a 10Ghz Tejas is because Intel never foresaw the end of process shrinks yielding free performance benefits. Process geometries only increase the ammount of chips/wafer lately. It takes other innovations to actually increase the device speed/power characteristics. High outputs of chips/wafer let Intel build up 3.4billion (one entire quarter) in inventory. High performance/power characteristics is part of what allowed AMD to help Intel reach this milestone of mediocrity. There's your best indicator of whether or not AMD is a better manufacturer.

I wasn't annoyed. I am now. Not because you may disagree, but because you expect me to keep spoon feeding you this stuff. Watch the presentation. Read the slides. Then do some of your own D&D and quit expecting me to donate my time to discuss topics you are unwilling to study yourself, even after I have provided you with the resources.


You know, part of my job is having to dicern good data from the bad. This is definatly bad data. People pulling junk out of their asses like this is how misinformation gets spread. Why the hell are you pulling data from this website? It doesnt look exactly . . . trustworthy.

Rofl, I saw the APC thing in another thread too. A computer that automatically makes your yeild go up?! And here this whole time we've been using engineers. What fools we've been.