I don't pretend to understand anything in here, but hopefully this thing overclocks like a dog.
Me, too!This thread is awesome for me because I usually read/post in threads/stickys to try to do three things only:
1) Learn something
2) Help someone/answer OPs questions
3) Ask a question
Thank you gOJDO for the thread very informative even though I don't understand most of this stuff.
I only hope that the lack of benchmark data from AMD prior to launch is due to them shocking us all with a major improvement over Intel. I'd hate barcelona to suffer the same fate as the 2900XT.
Me too. What's wrong with the 2900XT? I thought the only issue was that people were comparing it to the 8800GTX, when the 2900XTX was meant for that comparison.
Now if you can add some Doom 3 benchies, we'd be good to go!
------------------------------djcoolmasterx - "Ofcourse there is nothing that you are doing that will use that kind of power, beacuse you don't have that kind of powr to do things with."
Reply to Falken699
Everything you need to know about the new K10 architecture that will be used by forthcoming AMD processors, like Phenom and Opteron "Barcelona", including roadmaps
Is this designed to compete (and beat) the C2D/C2Q or Penryn?
------------------------------And on the third day, God created the Remington bolt-action rifle, so that Man could fight the dinosaurs. And the homosexuals.
Reply to spaztic7
It is designed to compete with (and possibly beat, I'm not sure on that one...) the C2D/C2Q. I think Penryn is likely to beat K10.
Then for the sack of argument... what’s the point! Is AMD saying by not going to the high end that they give up? Are they admitting that they are second best? This is a sad, sad day if this is true.
Then again, it is AMD's own fault for waiting untill Intel caught up/ surpased them.
------------------------------And on the third day, God created the Remington bolt-action rifle, so that Man could fight the dinosaurs. And the homosexuals.
Reply to spaztic7
the only data that is relevant is that a barcy is only at most 15% faster than an X2 when processing a single thread or even a pair of threads. That means that a barcy 2350 (for $400) is no better than a $102 X2-4800 for all single and dual thread applications. That is unbelievable.... it means that AMD is essentially abandoning the desktop market.
Message edited by shadowmaster625 on 09-11-2007 at 11:10:09 PM
yeah, it's is pretty logical to assume that AMD can keep up with Intel when it comes to R & D with a very small amount of capital in comparison to what Intel is working with.
Shadowmaster625,
stop being a fanboy.
Message edited by weskurtz81 on 09-20-2007 at 09:51:51 PM
Quad-core - Native quad-core design
- Redesigned and improved crossbar(northbridge)
- Improved power management
- New level of cache added, L3 VICTIM
Power management - DICE(Dynamic Independent Core Engagement) - PLLs for each core, clocked independently and varies clock speed depending on usage.
- ODMC power management: ability to shut down read channels if memory is only using writes and vice versa:
* Reduces the power consumption of the memory controller by up to 80% on "many" workloads.
- Aggressive grained clock gating
- Power management state invariant time stamp counter (TSC)
- Enhanced AMD's PowerNow - works independently without OS driver support
Virtualization improvements - Nested Paging(NP):
* Guest and Host page tables both exist in memory.(The CPU walks both page tables)
* Nested walk can have up to 24 memory acesses! (Hardware caching accelerates the walk)
* "Wire-to-wire" translations are cached in TLBs
* NP eliminates Hypervisor cycles spent managing shadow pages(As much as 75% Hypervisor time)
- Reduced world-switch time by 25%:
* World-switch time: round-trup to Hypervisor and back
Dedicated L1 cache - 256bit 128kB (64kB instruction/64kB data), 2-way associative
- 2 x 128bit loads/cycle
- lowest latency
Dedicated L2 cache - 128bit 512kB, 16-way associative
- 128bit bus to northbridge
- reduced latency
- eliminates conflicts common in shared caches - better for virtualization
Shared L3 cache - 128bit 2MB, 32-way associative
- Victim-cache architecture maximizes efficiency of cache hierarchy
- Fills from L3 leave likely shared lines in the L3
- Sharing-aware replacement policy
- Expandable
Independent DRAM controllers - Concurrency
- More DRAM banks reduces page conflicts
- Longer burst length improves command efficiency
- Dual channel unbuffered 1066 support(applies to socket AM2+ and s1207+ QFX only)
- Channel Interleaving
Optimized DRAM paging - Increase page hits
- Decrease page conflicts
Re-architect northbridge for higher bandwidth - Increase buffer sizes
- Optimize schedulers
- Ready to support future DRAM technologies
Write bursting - Minimize Rd/Wr Turnaround
DRAM prefetcher - Track positive and negative, unit and non-unit strides
- Dedicated buffer for prefetched data
- Aggressively fill idle DRAM cycles
Core prefetchers - DC Prefetcher fills directly to L1 Cache
- IC Prefetcher more flexible
* 2 outstanding requests to any address
HyperTransport 3 - Up to three 16bit cHT links
- Up to 5200MT/s per link
- Un-ganging mode: each 16bit HT link can be divided in two 8bit virutal links
- Can dynamically adjust frequency and bit width to save power
- AC mode (higher latency mode) to allow longer communications distances
- Hot pluggable
CPU Core IPC Enhancements: Advanced branch prediction - Dedicated 512-entry Indirect Predictor
- Double return stacksize
- More branch history bits and improved branch hashing
History-based pattern predictor 32B instruction fetch - Benefits integer code too
- Reduced split-fetch instruction cases
Sideband Stack Optimizer - Perform stack adjustments for PUSH/POP operations “on the side”
- Stack adjustments don’t occupy functional unit bandwidth
- Breaks serial dependence chains for consecutive PUSH/POPs
Out-of-order load execution - New technology allows load instructions to bypass:
* Other loads
* Other stores which are known not to alias with the load
- Significantly mitigates L2 cache latency
TLB Optimisations - Support for 1G pages
- 48bit physical address (256TB)
- Larger TLBs key for:
* Virtualized workloads
* Large-footprint databases and
* transaction processing
- DTLB:
* Fully-associative 48-way TLB (4K, 2M, 1G)
* Backed by L2 TLBs: 512 x 4K, 128 x 2M
- ITLB:
* 16 x 2M entries
Data-dependent divide latency Additional fastpath instructions – CALL and RET-Imm instructions
– Data movement between FP & INT
Bit Manipulation extensions - LZCNT/POPCNT
SSE extensions - EXTRQ/INSERTQ (SSE4A)
- MOVNTSD/MOVNTSS (SSE4A)
- MWAIT/MONITOR (SSE3)
Comprehensive Upgrades for SSE - Dual 128-bit SSE dataflow
- Up to 4 dual precision FP OPS/cycle
- Dual 128-bit loads per cycle
- New vector code, SSE128
- Can perform SSE MOVs in the FP “store” pipe
- Execute two generic SSE ops + SSE MOV each cycle (+ two 128-bit SSE loads)
- FP Scheduler can hold 36 Dedicated x 128-bit ops
- SSE Unaligned Load-Execute mode:
* Remove alignment requirements for SSE ld-op instructions
* Eliminate awkward pairs of separate load and compute instructions
* To improve instruction packing and decoding efficiency
Most of the informations are from Ben Sander's presentation at AMD FPF 2006, but also there are other informations included from various internet sites.
P.S. Any additional data or informations will be highly appreciated
So the socket 1207+ fasn8 systems are still a go according to this chart, is that right?
------------------------------Q6600 (overclocked to 3.2ghz) GAp35-DS-3L mobo, 8BG G-SKILL ddr2-1066, gigabyte gts 250(1GB), 2x dvd burner,320gb hard drive,640gb hard drive, black antec p182 case with corsair 750 watt psu.
Reply to reconviperone1
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