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You guys are absolutely right about the IMC frequency, but remember that it also has limitations - the faster IMC runs (stable!!!), greater the chance that you might saturate the memory bandwidth. If you come to this situation, the bottleneck becomes hardware design...

For me, the author obviously messed up entirely.

For Phenom, I think that proper software design (aware of the characteristics of NUMA) and corrected cache latency (B3) will help more than plp are saying. Larger caches from a die shrink (45nm?) or re-design will certainly have less influence - no matter the cache size if the core logic gives high latency cache access or has a faulty prefetch algorithm (which induces elevated cache misses).

I think that with proper software design, Phenom B3 will give some 20% increase in performance (at least, to the code I am working on).

But if that happens... it will make many people in this very forum cry and complain.

Oh wait... they do that now and they'll continue to do that. Nevermind. Carry on.

LOL, you're right...

Just to add, has anyone read this: http://techreport.com/articles.x/13633/4

They go straight to it.

Caveira209 9

Nice find thats exactly what we have been talking about. The biggest improvments to Phenom would come if the IMC clock is increased and the L3 cache removed and replaced with larger L2.

I'm convinced now that Phenoms performance hinderances are actually due to memory controller speed.

From what I can tell after installing the Phenom, HTT speed is tied to the IMC's speed. In this case for retail phenoms its tied at 2x the mem controller clock. 1.8Ghz Mem controller for 3.6Ghz Hyper transport speed. This is according to the bios on my K9a2 platinum. And also displays this way in AMD Overdrive utility.

Since installing the 9600 BE There are new options that have appeared in the Cell menu in the bios. About 4 for the cpu core, and 4 or 5 for the Northbridge/IMC. Once I have the time I'll post what they are, cause I'm gonna need help interpreting them. So I'll likely not try to OC until I get those figured out. Tried to mess around with AOD but it didn't work out properly, has some kind of issues setting the voltages. Though that may be due to the fact I originally installed with the x2 4200+. I also can't for the life of me find the option that allows you to disable the TLB patch, though not sure if that comes default on the 1.1 bios on my board.

I'm also coming to believe that the TLB erratum is probably what is causing them to limit the IMC/NB speed to 1.8 instead of full core speed. I believe if the IMC were running at core speed, the phenom may be able to give a core2 quad a run for its money.

I read the article and actually used my windows calculator to calculate theoretical results between 2.2 and 2.8 ghz cores. Which should be 1:0.785
Looking at the figures then makes me wonder if its not just the adulthood of the athlon core and the chipsets and bioses, drivers, compilers which causes a more steady scaling. If every time there is a small loss compared to theoretical scaling this is evidence of soms lack of horse power being applied to the application this could badly tuned drivers, bios and chipset. Considering this, i found that also many tests score better than the theoretical scaling which then makes me consider if the extra horse power proves windows is an inefficient os to do such tight tests. Since extra services and daemons running in background take a consideral amount of time during their routines. The memory controller would only bump up these figures on higher clock speed for the Phenom because it has a higher bandwith. And 1:1 performance scaling works as long as the bottleneck is the pure processing power. And in most these synthetic tests the phenom reaches a tad more or less then 1:0.785. Which i consider to be as expected. And the small difference between the athlon and phenom core i consider to be adulthood as ofcourse the phenom will produce better results as it is clocked higher and brought under circumstances when lets say HT2 vs HT3 will become relevant, obviously. And ofcourse in multicore environments the phenoms better architecture will whipe athlons butt. But since this article is a 1 core adventure my guesses are the small performance deficiencies indicate adulthood.

Luckilly i have all the time in the world to see Phenom peak out and sadly AMD has not. So lets hope B3 at 3+ghz and better support from motherboard manufacturers will bump AMD next to intel, so we get an equal "price" scaling across the board. As i hate intel for selling their qx6400 for $200 and their extreme for $2000 and its only 500mhz faster. I get more mhz in a couple minutes of clocking and tweaking.

I read some of the discussion here about intel or amd fanboys, i use both and i am indifferent to platform. They all perform too marginal for my needs. I don't have batch tasks to give to my workstations all day. I like my foreground application(s) to run smoothely and my background tasks to finish at the end of the day not hindering my foreground apps. Both intel as amd deliver processors which can fulfill some of my demands and there is no bias in this. If it comes down to shear pleasure of a game then cpu is less important and videocard is everything. This is my penny for a thought. I never seen a quadcore beat a highly clocked dualcore in any game when good videocards are used. So if this article is about processors then it might be about people who are going to use the processor power and i agree with caveira that Toms has to be impartial. If you compress Divx all day long you'll notice that intel is faster and if you do number crunching you'll get more out of AMD without a doubt. If people at toms think all you buy a processor for is to play crysis then i admit, get a core2 and push it to 3.4-3.7 ghz. If you want to be able to compress video while downloading and decompressing very large files, whilst playing a game and not noticing any degree of stuttering or performance loss i'd go for amd, because it has huge memory throughput where intel won't let you rape its fsb like this without stuttering. But this article is not about just 1 app but about a platform.

Your right the cpu forum is a bit of a playground most of the time

Good article.

I notice the Windows Performance Index is used.
Is the Windows Performance Index a REAL benchmark?
Not just looking up model numbers?
So a high Graphics Index will always mean a high 3DMark06 or game FPS (CPU & RAM independent) ?

If the WPI is a real benchmark, then I can take it more seriously.
Even though this should be updated so a 5.9 should mean good performance in Crysis for example. Will there be a 6 and 7 index soon so current high-end games can better display what's needed for min-requirements, recommended requirements, and max requirements.
Also for DIVX and 3D studio can use this.

Actually, there is no need to remove the L3 cache, nor to make L2 larger. The need is to reduce L3 latency (which is exactly the temporary "correction" given by the TLB updates of B2 stepping).

enewmen, if you liked it, ok, it is your opinion. But I trully missed the point that could make me conclude the same as you...

Interesting points. By the way, how many people have these Phenom clusters in their homes?

I think the author did a great job!! He set out to compare PHENOM to ATHLON and did just that. He found tested to see what asingle coreof each could do - and how well it scales from single to dual and then to Quad. Job well done.

What does Opteron (Barceona) or Xeon have to do with this article? NOTHING!

An Intel Q6600 will murder Phenom 9000 chips in 90-95% of desktop applications. AND it's 65nm - imagine what those 45nm will do to Phenom!

If AMD removes the L3 they will need to share the L2 between cores.

Whether or not the size needs to be increased would depend on how well it runs.

After a cache reaches a certain size if you still see speed improvements by going even larger... then you need to redesign your cache code... because something is not working properly. I would much prefer a small cache with efficient code... to a really big cache that is not as efficient.

soo would you say that the 6mb on intel 45nm core 2 duos is approaching the upper limit of an efficient cache? just interested.

Not "upper limit of efficient cache". Larger caches are good, but useless with low memory bandwidth, which can become the main bottleneck.

As an example, CELL BE (imo the best processor around, and a "lobotomic" version is used in PS3's) uses only 256kb of (some sort of) cache-like memory to every of its cores and is something like 5.5 or 6 times faster than xeon 54xx (45nm) with 12mb cache.

Again, it is all a matter of chip design - Intel's current x86 implementation has a very poor memory bandwidth compared to the core processing units.

Just to add --> intel uses 6mb of cache per pair of cores (it is wrong to count them together), and it is a "brute force" solution, in a sense that a larger program can be entirely allocated in a fast access memory. If this is a serious performance issue, one could re-design the chip (what AMD did when introduced Barcelona) instead of using more cache (what intel is making with C2).

I'd say that 512k-1Mb per core should have been approaching the limit of an efficient cache. If it didn't... then there is something wrong with how the cache was coded and it needs to be fixed. Otherwise they are using the cache as something other than the purposes of a cache.

Bad example... but something to consider:why do many performance hard disks have 16Mb of cache and not 512Mb or 1Gb? Perhaps because the added memory didn't speed it up because they have efficient code and don't need more memory. (I'm sure they tried more memory and ran into diminishing returns.)

Gee... do you mean when Intel changes to a monolithic core with onboard memory controller... adding more cache won't really help them as much as it seems to now?

Not that bad example: caches are used in a way to hide latencies and to improve error-free instructions, and hd's now equip cache for this reason.

I have already given an answer to this:

Intel with on-CHIP IMC is a chip re-design strategy, not simply get a known implementation and add more memory.