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Where did you get that idea from?
K10 is as close to K8, as K8 was to K7. There are a lot of major changes. It's just not possible to have fewer transistors per core, while adding 128 bit SSE, a lot of prefetch, a new fpu system with lower latency, improved OoE execution and on and on.
That in itself is part of the problem. If the hardware weren't so diferent, the optimizations made for K8 would work on K10.
Remember that before core2 was released, Intel gave it's software crew about 3 months to go around to the major software companies. I'm sure it was a lot of help in making programs work well and fast on core 2 tech.
Amd does not have the same type of support. They rely on the software co. being able to get the optimizations themselves. It takes longer to see all of the results of a new architecture.
Eventually it will come out that K10 is faster, clock for clock than core 2 quads.
It just wont help that much since Intel has such a comanding lead in process technology.

If my memory serves me right, SOI only reduces junction current leakage, which is increasingly becoming the least part of the problem. The other two major leakages, gate leakage, and substrate leakage, are the main sources of current leakage.

Intel skipped SOI because it could not be scaled high enough to be used on Pentium 4s. As Intel's own study showed, SOI transistors will have lower thermal only to a point, then thermal would skyrocket afterwards. Ironically, Intel completed the SOI study before AMD even implemented SOI on their processor. (I'll find that article for you)

EDIT: Scratch that. I no longer have the address of the website due to some technical difficulties with the private messages.

I'm still trying to find the article where it explains the three types of current leakage, and how HK/MG will rectify those.

I'm also trying to find information on DSL (dual stress layer) you mentioned earlier. I have no doubt it will be used in junction with SOI to curb current leakage, but I'm afraid its effectiveness will not be as great as HK/MG. Bottom line: HK/MG is needed to scale to 45nm and less.

SOI is useful only for substata leakage.
HK or high resistance chanel prevents most leakage between gate and drain, and source and drain, and inhibits transistor to transistor leakage. Substrata leakage has not really been a problem for Intel because they use a lower source voltage.
substrata leakage is caused be dissimilar voltages at the transistor and on the connects.
DSL is a new type of strained silicon. They put dynamic presure on the silicon latice to enhance electron flow, ans the other for hole flow. It does nothing for leakage.
You need IEEE membership to get the best articles about DSL.

I'm not sure if substrata you mentioned is junction leakage I mentioned, but this is my source.
http://www.semiconductor.net/article/ca6464480.html

Also, I'm not sure if HK/MG reduces transistor to transistor leakage, as it belongs to the interconnect. Maybe you can shed some light on that one.

This sounds like a substrate leakage to me, which SOI should not have significant affect of. I'll search around for its information.

Just a quick google on the internet, and it said DSL was developed as early as 2005. AMD originally wanted to use it on its 90nm X2 line.
http://www.newelectronics.co.uk/ar [...] train.aspx

But yeh, some additional information regarding DSL would be greatly appreciated.

I'll look up the info on those for you and me when I get home. Also why didn't you find that awesome video Intel had on HK/MG vs SOI? It was funny.

If you mean junction capacitance, then yes, it is the source for that type of leakage.

Again, it is a question of capacitance, or stored charge. HK reduces capacitance.

As voltage is applied to the junctions and transistors, they push a charge back into the silicon. When a dissimilar charge is applied nearby, those electrons/wholes leak to the new charge. SOI is basicly a shallowing of the available silicon behind the transistors and junctions. Less depth, less free electrons/holes to store a charge

Just a quick google on the internet, and it said DSL was developed as early as 2005. AMD originally wanted to use it on its 90nm X2 line.
http://www.newelectronics.co.uk/ar [...] train.aspx

But yeh, some additional information regarding DSL would be greatly appreciated.[/quotemsg]

come on AMD! Make a decent processor. Intel has already sold me out on my next processor (e8400), but if you can get a decent processor out by then I'll be there for the AMD Athlon 128 X8 12000+

Little off the subject but there already IS a 16 core processor coming out in 2009......called ROCK

http://en.wikipedia.org/wiki/Rock_processor

first successful boot of the Rock was in May 2007 on a Solaris system!

Look at this. 80 cores and was booted and tested against a 130 CPU servr. Beat it. Stock clock of 2.5GHz using 62w and 1TF of datd thouroghput. Can be clocked to 5GHz and double the thouroghput as well.

I'm guessing you meant to link to an article about Intel's Terascale processor.

http://www.pcper.com/article.php?aid=363

I see this differently.
AMD was able to make the "true" quad-core before Intel and had more time to tweek it, un-cork the power, iron-out bugs, etc. Even though the performance wasn't so good (even now)
So, if AMD CPUs will be killer, I'll wait until the next-gen chips. Then I will see if things get tweeked like I said.
If so, I will fully belive the bulldozer is for-real.

Thanks. I couldn't find it. But at least the wiki link has a link to Intels Terascale page

Um Intel has been working on Nehalem for quite a while so I am doubting they will have any problems with a "naitive" quad core. Especially considering they were able to create a true 80 core CPU. Intels R&D is gigantic remember that.

Not that I am futing Bulldozer but its a ways away and we don't know much about it yet.