This “all-gate approach” utilizes a “forest of nanowires all under control of the same gate.”
It has been well established that as transistor sizes continue to decrease, planar technologies are reaching their limit. Thus far, we’ve seen technologies such as FinFET be introduced to partially alleviate this problem.
A team of researchers from the Laboratory for Analysis and Architecture of Systems in France is focusing on a new approach that utilizes a “forest of nanowires all under control of the same gate.” According to IEEE Spectrum, this design is composed of an array of 225 doped-silicon nanowires where each wire has a 14 nm chromium layer surrounding its midsection that serves as the gate.
Promisingly, the design’s manufacturing process doesn’t involve any complicated lithography. The researchers plan to eventually develop IGA nanowires because of their better electron mobility. Though the nanowire forest design is certainly more complex than the aforementioned FinFET transistor design, it could potentially be simplified by reducing the total number of nanowires needed to develop the transistor.