Santa Clara (CA) - Intel today said that a 4-way server system based on the upcoming Montecito dual-core processor outran a 4-way RISC-based system by about 60 percent in a benchmark test.

Intel is aiming for the top with the next Itanium processor, codenamed "Montecito". The dual-core 64-bit chip will not only be the most complex CPU ever built, but also offer a substantial speed increase for high-end servers, according to Intel. The company announced that a 4-way system based on Montecito chips posted a floating point performance of 45 GFlops in the Linpack benchmark. This trumps the previous record holder in this segment, a RISC-based 4-way server that achieved 27.5 GFlops. A similar performance was shown by a Montecito system at the recent International Supercomputer Conference (ISC) in Heidelberg.

"This performance result gives a peek into the advantage Montecito is expected to have over previous generations of the Itanium architecture for high-performance computing applications," said Phil Brace, general manager of Intel's Server Platform Group. "Three years ago we showed a four-processor Itanium-based system at 11.43 GFlops, and two years ago we hit 22.7 GFlops." According to Brace, a TFlop performance can be expected in 20-server clusters.

There are few confirmed facts about the Montecito processor. What we know so far is that the chip will contain 1.7 billion transistors, come with clock speeds of at least 1.6 GHz, support Hyper-Threading and integrate up to 2x12 MByte of on-die cache. Thermal design power of the chip (TDP) will drop from currently 122 to about 100 watts. Average power consumption is likely to be significantly lower, since Intel will introduce adjustable clock speeds similar to the SpeedStep technology the company uses in its mobile processors and the Pentium 4 600 series.

Montecito is expected to make its debut late this year or early in 2006. Following Montecito, Intel will release "Montvale" and "Tukwila". Tukwila is expected to be a "many-core" processor with at least four cores per processor.

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