Toshiba Sampling 64GB UFS-Based NAND chips
Toshiba is now shipping 64 GB NAND flash modules using the UFS interface.
Toshiba said last week that it began sampling out new 64 GB embedded NAND flash memory modules packed with a UFS interface (I/F). Designed for a wide range of small form factor products like smartphones and tablets, the new module is fully compliant with the JEDEC UFS v1.1 standard and supports the use of "lanes".
"The JEDEC UFS Ver.1.1 compliant interface handles essential functions, including writing block management, error correction and driver software," Toshiba said. "It simplifies system development, allowing manufacturers to minimize development costs and speed up time to market for new and upgraded products."
The company said the new modules are sealed in a small FBGA package measuring a mere 12- x 16- x 1.2-mm and uses 169 balls. Voltage ranges from 2.7V to 3.6V for the memory core, 1.7V to 1.95V for the controller core, and 1.10V to 1.30V for the UFS interface signals.
The UFS serial interface has scalability the in number of lanes and speed. Toshiba's new modules offer single upstream and downstream lanes with 2.9 Gbit/sec bandwidth. Samples now shipping are mainly intended for evaluation of the UFS interface and its protocol in host chipsets and by OS vendors.
"Demand continues to grow for large density, high-performance chips that support high resolution video, driven by improved data-processing speeds in host chipsets and wider bandwidths for wireless connectivity," the company said. "Toshiba has proved itself an innovator in this key area, and is now reinforcing its leadership by being first in the industry to support samples with a 64GB UFS module."
Commercialization will depend on how receptive OEMs will be with these new chips using the UFS standard, so stay tuned.

Give it 5 years and Intel will integrate this into their CPUs...
But actually...if what you're saying is correct...it would be kind of cool, to have one of these as an expansion card to your mobile devices. Increase RAM and storage simultaneously.
Those balls are still "small balls"...geddit?
http://en.wikipedia.org/wiki/Flash_memory#Limitations
http://en.wikipedia.org/wiki/Flash_memory#Limitations
http://en.wikipedia.org/wiki/Flash_memory#Limitations
Why is it so difficult to detect and eliminate duplicate comment submissions?
Why is it so difficult to detect and eliminate duplicate comment submissions?
Well, they could do something more like PCIe with multiple serial lanes, granted I still wouldn't want flash memory to replace DRAM. Flash's increasingly poor endurance with every process shrink and bits per cell increase would probably only help planned obsolescence supporters.
Many SoCs have memory bandwidth in several GB/s. Going down to a few Gb/s is a huge downgrade in performance. No, these memory chips are not half the transfer rate of current LPDDR2 memory. As is, memory bandwidth of mobile devices is often one of the greatest bottle-necks for performance, so such a step back or even going with what I said above to maybe get similar performance is not the trend that is needed right now.