Cadence Announces First DDR4 Controller and PHY IP in 28-nm
Electronic design automation company Cadence said that it has qualified its DDR4 SDRAM physical layer (PHY) and memory controller design IP in TSMC's 28-nm production process.
Cadence recently announced that it has developed "multiple" versions of its DDR PHY and controller IP based on advanced drafts of the DDR4 spec published by JEDEC.
"DDR4 is going to be the next big thing in DRAMs, but its signaling is challenging to handle," said Jim Handy of Objective Analysis in a prepared statement. "As PCs migrate to DDR4 DRAMs, this standard will become the volume leader, giving it a price advantage that will be impossible to ignore. ASIC designers who want to take advantage of that pricing are likely to need a lot of help putting a reliable interface on their products."
Cadence said that its PHY exceeds the data rates described by the DDR-2400 draft, but did not reveal what speeds have been achieved. The company also announced that it has a "low-power, all-digital mobile PHY implementation that exceeds the data rates called for in both the DDR-1600 and DDR-1866 DDR3 standards and the maximum data rate of the low-power LPDDR2 standard."
Cadence said that its DDR4 memory controller technology and PHY IP is available now.