Palo Alto (CA) - Hewlett-Packard (HP) today released first details about a "hybrid" nano-CMOS chips that could lead the way not only to much smaller chip structures and extend the physical limits of Moore's law, but also continue the trend to a substantial decrease of power consumption in semiconductors.

The company said that its research results could lead to a new type of field programmable gate arrays (FPGAs) that are up to eight times denser that today's devices. The foundation of the technology is a crossbar switch structure, called "field programmable nanowire interconnect (FPNI)," that is placed on top of conventional CMOS (complementary metal oxide silicon).

"As conventional chip electronics continue to shrink, Moore's Law is on a collision course with the laws of physics," said Stan Williams, an HP senior fellow at the Quantum Science Research division of HP Labs. "Excessive heating and defective device operation arise at the nanoscale. What we've been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices."

HP's FPNI allows all logic operations to be processes in the CMOS, whereas most of the signal routing in the circuit is handled by the crossbar. "Since conventional FPGAs use 80 to 90 percent of their CMOS for signal routing, the FPNI circuit is much more efficient," HP claims. Also, the company said that the density of transistors actually used for performing logic is much higher and the amount of electrical power required for signal routing is decreased.

So far, Williams team has only simulated the technology on the computer screen, but HP claims that, in a "conservative" chip model, a 15 nm crossbar and 45 nm CMOS could become a reality by 2010. A 4.5 nm crossbar shrink could be possible by 2020, according to HP's estimates. HP expects to be able to present an actual working prototype of an FPNI chip "within the year."

If successful, the FPNI approach could result in much lower power consumption of semiconductors, according to Williams. A 4.5 nm crossbar with 45 nm CMOS would yield a hybrid FPGA about 4% the size of a 45-nm CMOS-only FPGA. Such a structure is likely to use a lower clock speed and consume less power as a result. Performance enhancements could be achieved "with lots of parallelism."

The downside of the crossbar shrink is its size - smaller nanowires and crossbars are expected to carry higher defect rates. However, HP said that even with 20% of the nanowires broken, a FPNI chip would still be 75% effective.

Source : Tom's Hardware US