New Intel 65 nm lithography promises reduced leakage for small devices
Santa Clara (CA) - In a further demonstration of Intel's renewed focus on power conservation over performance where necessary, the company is announcing the addition of a new, alternative lithography process for the 65 nm category that stresses orders-of-magnitude reductions in power leakage.
Yesterday, Intel unveiled its "P1265" 65 nm lithography process, exclusively for ultra-low-power devices that require small size, though not necessarily the highest performance. ("P1264" refers to the company's existing, high-performance 65 nm process.) A common problem among small-scale components when deployed on small-scale platforms, is power leakage - essentially, wasted energy. As Intel's technology analyst for its Technology and Manufacturing Group, Rob Willoner, told Tom's Hardware Guide , Intel has always had three ways of addressing the power leakage problem. "These are well-understood problems," Willoner told us, "and it has always been known that we could reduce this leakage, but then we also reduce the performance." In ever-smaller devices, the ratio of what we normally attribute as "power consumption" to actual power usage may be getting smaller, and that's dangerous.
In a transistor - tens of millions of which are included in a modern dual-core CPU - the flow of electrons is coaxed from a source toward a drain , forcing it along the way to cross a gate that would otherwise serve as an insulator. As Willoner demonstrated, there are three primary causes of power leakage at the transistor level, all of which are fairly traditional. One such cause is "source-to-drain leakage," which refers to electrons that are compelled by the doping element in the drain, even when the transistor state is supposed to be Off.
Three common sources of transistor power leakage, and Intel's solutions. (Courtesy Intel Corp.)
"As the geometries get finer," said Willoner, "the source and drain are closer together with each process generation. [So] that gap is narrowed, and you find current flowing through there even when the transistor is supposed to be in the Off state. We obviously don't want that; it's analogous to having your [household] light going to dim mode rather than off mode. You want it to be completely off."
Second is so-called "junction leakage" from either the source or the drain into the silicon substrate, which literally happens to some degree all the time. The third cause of leakage concerns the insulator bar at the gate. With each new lithography process generation, Intel has generally made that layer thinner - recently as thin as a mere five atoms of thickness. That enables a higher-performing, faster-switching transistor," said Willoner. "But as we make it thinner, electrons leak through - it becomes porous. That's another undesirable effect."
Intel's solutions to these problems, according to the company, will reduce apparent leakage to as much as one one-thousandth of the measured amount with existing P1264. The source-to-drain leakage problem, for instance, is tackled by increasing the threshold voltage of the transistor - the amount of voltage necessary to trigger the transistor into the On state. This is done by adjusting the doping concentration at the drain.
Junction leakage is addressed through a technique called "low-damage junction engineering. "We're changing the profile of the source and the drain," explained Willoner. Traditionally, the profile looks like the cross section of an old, ceramic bathtub; P1265's new shape is, for now, a company secret. But the new shape will dramatically reduce the dropoff rate, so that unused electrons literally no longer slip into the tub.
The insulator leakage problem is addressed using "common sense," as Willoner explained it: increasing the oxide thickness of the gate dielectric.
As an insurance policy of sorts against further leakage, P1265 opts to tighten and make narrow its wire interconnects. Normally, these wires are made fatter to increase performance; with P1265, the interconnects are thinner, and their pitch is tighter. With this adaptation comes an actual payoff: The die size can be reduced by as much as 10%. As Intel spokesperson John Casey told us, "What looks like a small difference in that interconnect foil actually can make a significant difference to die size."
Willoner added that yields - the number of good chips produced per die - actually increases at a non-linear rate as die size is reduced. "So when you make the die 10% smaller," he remarked, "your yield is much better than 10%.
"You have to have a balanced design," Willoner continued. "So if your transistors don't need to be so fast, then there's no need to make the interconnect super-fast. If you [do that], you're leaving money on the table. Your overall performance will be determined by the transistor performance. So we might as well make the interconnect a little bit slower by making its cross-sectional areas smaller."
The die size reduction, Intel told Tom's Hardware Guide , will also compensate for new production costs, thus keeping the street price of new ultra-low-power CPUs down.