Sequence said that it had reached a milestone in its recent power optimization efforts using its MTCMOS (Multi-Threshold CMOS) technology. The company claims to be first to become the EDA industry's first organization to achieve power-gating optimization by reducing leakage on a 90 nanometer design.

According to the firm, MTCMOS power-gating works to reduce leakage currents by disconnecting the power supply from portions of the circuit when those portions are inactive. Leaking currents are prevented by inserting a series switch transistor between the logic cells and the power supply or ground. The switch is closed when the logic is operational and opened when the logic is inactive.

Sequence developed and announced the technology together with Toshiba. The firms gave vague data, how effective the approach will be: "Reductions of 10x to 100x in leakage can be achieved by using this technique."

Leakage control has become a major design issue due to leakage currents that drain a battery's charge even when a wireless device is inactive or in standby mode. Transistors in each new process generation are leakier than those in previous generations due to transistor scaling effects.

Leakage is also an issue in active mode, when the transistors are operational, as any power wasted due to leakage is not available to be allocated to performance enhancing logic. (THG)

Source : Tom's Hardware US