The 64-layer 3D NAND about to land from Micron and Toshiba certainly sounds impressive, but it pales in comparison to what Sk Hynix is working on for future release. The company is developing 96-layer and 128-layer 3D NAND flash. The new flash won't be available for a few years, but that makes it no less exciting. We have yet to see 72-layer 3D from Sk Hynix in our lab, but it will begin shipping soon in the PC401 using 256Gbit TLC die, according to the UNH-IOL list of tested products.
The information we found about the successor to 256Gbit 72-layer 3D TLC shows 96 layers with 512Gbit die capacity. The follow up to that is a massive 1Tbit die from 128-layer TLC from the other South Korean SSD manufacturer with full vertical integration.
To put it into perspective, 1Tbit is the fancy way of saying 128GB. The die is a single piece of silicon, and NAND die are about the size of your pinky fingernail. You can see Micron's latest die in this article. It sounds like something Q made for James Bond in a movie script, but that's the NAND flash industry for the fab companies; they make the impossible reality, and the development cycle is rapid.
SSDs use several NAND die per product, and the act of reading and writing to several at the same time give us the performance we associate with SSDs. It takes several die to saturate PCIe 3.0 x4 in terms of throughput. The new large capacity die will use the same number of parts to reach a specific performance number, but the capacity of the drive will increase. In short, a 512GB SSD today will turn into a 2TB SSD with 1Tbit die. The cost of the two products should be fairly consistent, too. It's important to understand that we're talking about next-next generation technology here--that's two next generations out from now.
The part that makes this little nugget of information interesting also comes from some backroom conversations we had over the last few days. At Computex 2018, QLC with 4-bit per cell will enter into the NAND discussion from at least one NAND fab. QLC will increase die density by adding an extra bit. Single-level cell NAND had to look for only two power states, but that moved to eight with TLC. QLC will increase the number to sixteen states, and it will require significantly advanced error correction to stabilize the flash that's expected to have around 100 P/E cycles. It looks like Sk Hynix will not follow suit with QLC that early.
We don't want to make it sound as if Micron and Toshiba are not working on 128-layer NAND die. We just haven't found anyone willing to talk about what comes after 64 layers for TLC NAND from those companies.
