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UMC to Deliver 20 nm Chips in H2 2013

By - Source: Digitimes | B 16 comments

He expects a "structural shift", according to Digitimes, that will lead to a gradual change in market leadership.

Sun sees UMC well-positioned with new 300 mm production capacities coming online in 2013. The company is investing about $2 billion into its fabs this year, which mainly will be used to grow 28 nm capacity. Sun estimated that about 5 percent of UMC's 2012 revenues will be derived from 28 nm products.

20nm FinFET is scheduled for a 2014 volume production and the company said that it has an agreement with IBM to develop a 20 nm 3D FinFET production technology. Low-volume 20 nm chips will be coming off the production lines in H2 2013, Sun said.

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  • 0 Hide
    shin0bi272 , July 30, 2012 3:17 PM
    I have to ask... why they are still using round wafers to make square chips? You'd think that someone would have come up with a way to mass produce chips 1 at a time via some sort of assembly line process. If it works for food, light bulbs, cars, dishware, etc., etc., it should work for chips too. Eh anyway Im sure someone will figure it out some day.
  • 1 Hide
    blazorthon , July 30, 2012 3:21 PM
    shin0bi272I have to ask... why they are still using round wafers to make square chips? You'd think that someone would have come up with a way to mass produce chips 1 at a time via some sort of assembly line process. If it works for food, light bulbs, cars, dishware, etc., etc., it should work for chips too. Eh anyway Im sure someone will figure it out some day.


    Making larger wafers are generally cheaper per chip produced than making smaller wafers if I remember correctly. Round ones are probably much easier to make than square ones.
  • 1 Hide
    gilgamex , July 30, 2012 3:33 PM
    I think it's because the wafer is spun through all sorts of production phases, the circular shape of it allows the aerodynamics of it to be consistent leaving little margin for error.
  • 3 Hide
    gilgamex , July 30, 2012 3:37 PM
    gilgamexI think it's because the wafer is spun through all sorts of production phases, the circular shape of it allows the aerodynamics of it to be consistent leaving little margin for error.


    Ignore this is completely wrong, and honestly a guess, "Silicon wafers are grown by using the Czochralski, in which a 'seed crystal' is rotated in a bath of hot molten silicon. As the seed crystal rotates, silicon atoms stick to crystal with a specific orientation that forms a crystal lattice. Eventually, this crystal becomes significantly large and forms a ingot weighing several tons. Because the crystal was rotating, the edges appear form a circle, not unlike spinning a popsicle stick in a thick syrup." found this on a website
  • 3 Hide
    rantoc , July 30, 2012 3:43 PM
    blazorthonMaking larger wafers are generally cheaper per chip produced than making smaller wafers if I remember correctly. Round ones are probably much easier to make than square ones.


    You are correct, bigger wafers produces more chips per cycle and also a bit less waste in the cutting process (square chips on a circular wafer = unused parts).
  • 2 Hide
    Anonymous , July 30, 2012 3:59 PM
    If you bake a casserole or brownies in a square baking dish, the corners come out overcooked because they are, to put it simply, more exposed to the oven environment than the mid-sides areas and therefore heat up more quickly. That kind of non-uniformity is unacceptable in wafer processing, where temperatures and time-at-temperature needs to be precisely controlled.
  • 0 Hide
    blazorthon , July 30, 2012 4:03 PM
    Quote:
    You are correct, bigger wafers produces more chips per cycle and also a bit less waste in the cutting process (square chips on a circular wafer = unused parts).


    pcgeekesqIf you bake a casserole or brownies in a square baking dish, the corners come out overcooked because they are, to put it simply, more exposed to the oven environment than the mid-sides areas and therefore heat up more quickly. That kind of non-uniformity is unacceptable in wafer processing, where temperatures and time-at-temperature needs to be precisely controlled.


    Thank you for the clarification.
  • 0 Hide
    shin0bi272 , July 30, 2012 5:08 PM
    pcgeekesqIf you bake a casserole or brownies in a square baking dish, the corners come out overcooked because they are, to put it simply, more exposed to the oven environment than the mid-sides areas and therefore heat up more quickly. That kind of non-uniformity is unacceptable in wafer processing, where temperatures and time-at-temperature needs to be precisely controlled.

    I was thinking more along the lines of cooling rather than baking. check out how they make glass dinner ware (I think its called vitrelle)... using a process similar to that could work for making chips.

    http://science.discovery.com/videos/how-its-made-vitrelle-dishware.html

    You have molten silicon and you put it in a contraption that looks like a square waffle iron except its a cooling grid where each of the squares are the right size for the cpu die. The silicon goes in liquid and is spread out evenly then cooled on all sides by the waffle iron like device. Then you open the waffle iron and invert it and shake it and the chips fall out. Its not perfect no but if you could figure out a way to make the chips cool perfectly and get them out of the grid without breaking you'd have the ability to mass produce chips like lightbulbs ... Plus any waste could just be melted back down and repoured.
  • 0 Hide
    f-14 , July 30, 2012 5:42 PM
    shin0bi272I have to ask... why they are still using round wafers to make square chips? You'd think that someone would have come up with a way to mass produce chips 1 at a time via some sort of assembly line process. If it works for food, light bulbs, cars, dishware, etc., etc., it should work for chips too. Eh anyway Im sure someone will figure it out some day.

    watch on you tube at about 1:50 http://www.youtube.com/watch?v=aWVywhzuHnQ

    Mr Perry who is this "he" you are referring to at the beginning of your article? plagiarise much?
    He expects a "structural shift", according to Digitimes, that will lead to a gradual change in market leadership.
  • 0 Hide
    shin0bi272 , July 30, 2012 6:55 PM
    f-14watch on you tube at about 1:50 http://www.youtube.com/watch?v=aWVywhzuHnQ


    saw that a couple of years ago actually. One of the things that they cut out of that youtube clip (or was on the "how its made" version of the same video) was that only 3 or 4 out of 10 wafers actually make it without shattering. Id also like to point out that the only reason that the crystal in that video is circular is because the thing they put it in is circular. if the seed crystal is put in the middle it should be possible to do the same thing with a square retort.

    it should still be possible to take a smaller amount of silicon and put it in a mold with a grid on it and spin it while it cools and make a single crystal just square instead of circular.
  • 0 Hide
    phate , July 30, 2012 6:57 PM
    "UMC also set a goal of moving 20nm FinFET process to volume production in the second half of 2014"

    So by the time Intel is shipping 14nm, these guys will be shipping 20nm.
  • 0 Hide
    blazorthon , July 30, 2012 7:23 PM
    phate"UMC also set a goal of moving 20nm FinFET process to volume production in the second half of 2014"So by the time Intel is shipping 14nm, these guys will be shipping 20nm.


    Intel has their own excellent fabs and might be ahead of the other companies for as long as they're in business. This has been going on for quite a while now. You're not surprised by Intel staying ahead, are you?
  • 0 Hide
    ang1dust , July 31, 2012 12:54 AM
    I dont understand why we cant just skip to 5nm and add quantum mechanics.
  • 0 Hide
    blazorthon , July 31, 2012 2:27 AM
    ang1dustI dont understand why we cant just skip to 5nm and add quantum mechanics.


    There are several problems with that that even I know of. One such problem would be that such a huge jump would need a similarly huge leap in technology and that's more difficult than gradually moving on to smaller process nodes. Another problem is that it would be almost definitely be very expensive, even for multi-billion dollar companies, to do that. They would also not be making money from intermediate process nodes to make up for this.
  • 0 Hide
    mugiebahar , August 23, 2012 9:33 PM
    I dont understand why we cant just skip to 5nm and add quantum mechanics

    Ding Ding Ding Answer is "we don't know how"

    the only real reason is we have not invented nor have the knowledge or ability to do it. Intel pours Billions of dollars into research just to get to the next shrink. If Intel (I use them because they are ahead of the curve) could they would but they can't so they don't. Also it seems problematic right now as below 14nm there is too much cross noise and leakage that transistors would be screwed up. Not saying we can ho past that but we still need to figure it out, then multiply it across billions of transistors.
  • 0 Hide
    blazorthon , August 23, 2012 10:02 PM
    mugiebaharI dont understand why we cant just skip to 5nm and add quantum mechanicsDing Ding Ding Answer is "we don't know how" the only real reason is we have not invented nor have the knowledge or ability to do it. Intel pours Billions of dollars into research just to get to the next shrink. If Intel (I use them because they are ahead of the curve) could they would but they can't so they don't. Also it seems problematic right now as below 14nm there is too much cross noise and leakage that transistors would be screwed up. Not saying we can ho past that but we still need to figure it out, then multiply it across billions of transistors.


    You forget profits. Going from 22nm to 14nm to 10nm to 7nm to 5nm (or something like that) means several more generations that Intel and other companies get to profit from in addition to being easier to do than skipping nodes and technologies. So, even if Intel could, they probably wouldn't use smaller process nodes. Also, getting past the leakage issues and such would probably take different process components than the bulk CMOS processes use, at least in their current forms. SOI might help, but it might take something even better.