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• The deep dive session on Moorestown, Intel’s update to the wildly successful Atom processor, was heavily attended. Perhaps the most interesting aspect of Moorestown is how far it will distance itself from the PC. Moorestown's power consumption at standby will be reduced by up to 50x. Moorestown will be the core of a new line of SoCs (systems-on-chip) from Intel. So, unlike the current Atom, we may see many different instantiations of Moorestown products, aimed at highly segmented markets. The Moorestown platform will mainly consist of two parts: Lincroft (the SoC) at 45nm and Briertown. Lincroft will have the CPU, MIPI display interface, LP (low power) DDR memory controller, plus 2D/3D graphics and memory controller. Briertown is the second chip which has SDIO, audio engine, modem for 3G, and so on. Lincroft brings in the display and memory controller into the CPU die, plus graphics and video decode capabilities. The new CPU will have Hyper-Threading and “burst mode,” similar to Turbo Boost on Intel’s desktop and laptop CPUs. Power reduction is partly enabled by moving to the type of I/O infrastructure used in handheld and mobile devices, including SDIO, MIPI (for displays), and low power DDR memory. Also, the graphics and video decoders can run independently of the CPU at lower power. So graphics, video decode, and audio are fixed-function coprocessors. What’s being left out of Moorestown are PC interfaces. For example, MIPI is replacing LVDS as the display interface. PCI Express is out entirely. USB will be present, but not SATA I/O. If Intel’s goal is to segment Atom based netbooks so that they’re more limited than PCs, then Moorestown will accomplish this. On the other hand, it will be much more power efficient than a PC-like device, while maintaining Atom-like levels of performance. Turbo Boost We’ve talked about Turbo Boost in the past. Turbo Boost is a feature of Intel’s Nehalem CPU that allows the frequency of utilized cores to ramp up to higher clock speeds in order to bolster the performance of a lightly-threaded app. The limiting factor is TDP--thermal design power. As long as the overall CPU remains within the thermal budget, the core (or cores) can be pushed harder than the default frequency to get a bit more performance. With Intel’s upcoming Arrandale and Clarkdale 32nm dual-core CPUs (which support four threads via Hyper-Threading), Turbo Boost also affects the on-die integrated graphics core. Graphics Turbo will be introduced with Intel’s Arrandale 32nm mobile CPU. Intel is building in a “graphics turbo manager” that manages the power budget for the integrated graphics core. There will be a Turbo Boost driver that handles Turbo Boost across the two CPU cores and the graphics core. In the case of running a graphics-intensive application that’s not hitting the CPU very hard, then the GPU clock frequency scales up, just as it would on a CPU core affected by Turbo Boost. Currently, the Arrandale Turbo Boost driver will be a Windows 7 component, and only support the integrated graphics core. Should the laptop instead include a discrete graphics chip, graphics turbo doesn’t affect its performance. However, Turbo Boost still has some impact on the graphics chip, since the processor has PCI Express and memory controllers on board. The upshot of all this, from the point of view of companies building laptops, is that the design of the thermal solutions to keep notebooks cool are more critical than ever. Turbo Boost will keep the system running closer to the maximum thermal envelope. So, it’s important that Arrandale laptops have proper cooling solutions. Intel has data that shows the skin of the laptop (palm rests, the underside of the case) often become hotter than the actual CPU, which affects its overall performance envelope. A poorly designed cooling solution will mean the system won’t run at its maximum possible performance under Turbo Boost.

• Intel Developer Forum, Day One: Intel Thinks Small

  Things small include the next-generation desktop microarchitecture Intel is calling Sandy Bridge. If Westmere represents the transition of Nehalem’s architecture to 32nm, Sandy Bridge is the “tock”--a new microarchitecture on an existing process technology. It’s odd to call 32nm “existing,” but Intel has already built a boatload of 32nm CPUs already. Not much was revealed about the specifics of Sandy Bridge, however. Taking a step down the size scale to mobile platforms, Intel showed off Clarkdale, the 32nm mobile CPU that will offer an on-package graphics chip. Clarkdale, as with the current Core i7’s, will support Hyper-Threading, though it will have only two cores, rather than four. Clarkdale (in addition to all other Westmere-based products) features hardware-assisted AES encryption. Historically, the problem with high levels of encryption has been the performance hit incurred when encrypting or decrypting in real time. Intel hopes that its AES-NI (AES New Instructions) will enable more widespread use of encryption software. As mobile platforms become the mainstay of most computing users, the fear of losing valuable data to identity thieves increases. Intel showed one demo where a stolen laptop could be deactivated over the Web with the encrypted hard drive rendered completely inaccessible until the laptop is brought back to its IT department. One aspect of this focus is the Atom. Atom has become pretty popular for netbooks, but Intel’s real target market for Atom has always been mobile Internet devices and smart phones. The current-generation Atom isn’t well-suited for smaller devices like cell phones, which require extensive battery life and don’t (yet) need multi-GHz speeds. However, as the process technology moves to 32nm, the next-generation Atom (code-named Moorestown) will be built on smaller boards and offer greater integration than today’s Atom. Idle power will be considerably reduced, too--up to 50x lower power draw at idle than the Atom we now know. The whole affair is still a bit too large for all but the biggest smart phones, but as Atom becomes even smaller in the generation beyond Moorestown (code-named Medfield) Atom may be small enough for pretty small phones. Beyond 32nm While we’re talking about small, let’s talk 22nm. At one point during the morning keynote, Intel CEO Paul Otellini held up a wafer consisting of 22nm test SRAM chips. With 32nm CPUs just around the corner, Intel is already starting to push new technologies. In the tick-tock mode, Westmere is now practically old hat. Intel is starting to talk up its true next-generation microarchitecture, Sandy Bridge. On the process side, Intel displayed a wafer of SRAM (static RAM) test chips built on a 22nm manufacturing process, including its 3rd generation high-k plus metal gate technology. The 22nm SRAM chip has 0.092 um2 SRAM cells for high-density SRAMs, and 0.108 um2 for low voltage apps. The 0.092nm cell is the smallest working chip to date. Although it is an SRAM test chip, there are some logic circuits built onto the chip to test the process technology as it might be used to build actual microprocessor logic. Intel’s code name for the process for building CPUs is P1270; P1271 is the manufacturing process that will be used for SoC (system-on-chip) processors, including next-generation Atom processors. The “12” implies 12-inch wafer sizes; current tools don’t really allow Intel to move to larger wafer manufacturing sizes in the near term. One of the interesting aspects of Intel’s focus on process technology and Moore’s Law is the implications on the evolution of instruction sets and chip size. One slide from the afternoon keynote noted how the original Intel 4004 had about 70 instructions, whereas the current generation of Nehalem CPUs now have over 700 instructions. And, of course, that Nehalem CPU is physically no larger, even though the transitor count is vastly greater.