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28. Reduce CAS Latency

BIOS from A to Z
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When memory access is underway a particular time period must elapse between specifying a memory address and accessing its contents; this is called latency. This interval for a memory cell may be set to 2T for two clock cycles, 3T for three clock cycles, and so on. A smaller value for "SDRAM CAS Latency" means faster performance; higher means slower performance.

The safest and most correct value for "SDRAM CAS Latency" is usually printed on a label or etched directly onto the memory module itself. Typical values are 3T or 2.5T for lower-cost memory modules. Change this setting to 2.5T or even 2T, then test your system for stability. Some memory manufacturers claim that 2T-capable memory can also handle higher memory clock rates. If tightening CAS latency succeeds, you may also want to try boosting the memory clock rate by increasing the value for the "Memory Frequency" option.

Warning: Make only one change at a time, then reboot and test its effects by running a benchmark. This makes it easy to back off only the right value when instability rears its head and requires a rollback of some kind.

29. Reduce Memory Load Time

With the correct settings, memory cells acquire the electrical charge they need to operate more quickly. Set a value for the "SDRAM RAS Precharge Delay" option (in clock cycles) for the interval when the charge level is building and when the RAS signal is sent. Smaller values, such as "2", set the tempo faster than larger values, but larger values ensure more stable system operation. Reduce the number of clock cycles one at a time and test your system for stability after each such change.

30. Shorten The Delay Before The Next Memory Access

The "SDRAM Active Precharge Delay" option is also specified as a number of memory clock cycles. It indicates the delay between subsequent memory accesses, so reducing it can speed up overall memory access.

A typical rule of thumb for this value is: Active Precharge Delay = CAS-Latency + RAS Precharge Delay + 2 (added as a safety margin). As with other experimental value tweaks, reduce this number by one clock cycle at a time to determine if faster values work, as is often the case. As soon as stability problems appear, bump this value up by one to ensure trouble-free operation.

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