Page 1:Is Faster Notebook Performance Worth Shorter Battery Life?
Page 2:Yonah: Pentium M Successor With Two Cores
Page 3:..., Faster Front Side Bus (FSB),
Page 4:...and Other Important Enhancements
Page 5:Dynamic Power Coordination
Page 6:Dynamic Power Coordination, Continued
Page 7:Digital Media Boost
Page 8:I've Got A Core Duo Processor LV L2400. What Have You Got?
Page 9:Models And Pricing For Core Duo And Core Solo CPUs
Page 10:Overview Of All Centrino Generations
Page 11:New Chipsets And Two Different Southbridges
Page 12:Test System Configuration Details And Comparison Systems
Page 13:Benchmarks And Settings
Page 14:Extended Benchmark Suite
Page 15:ABBYY FineReader 8
Page 16:Application Test Results
Page 17:Windows Media Encoder 9
Page 18:Results From The Multitasking Scenarios
Page 19:Office Applications: SYSmark 2004 SE
Page 20:SYSmark 2004 SE, Continued
Page 21:Battery Life: MobileMark 2005
Page 22:MobileMark 2005, Continued
Page 23:Energy Drain: Graphics Chip Or Chipset?
Page 24:Summary And Conclusions
Page 25:Summary And Conclusions, Continued
...and Other Important Enhancements
Intel wouldn't be Intel if it didn't garnish the introduction of a new CPU model series with a bundle of new marketing buzzwords. In the pages that follow we'll shed light on these new terms:
- Smart Cache, Dynamic Cache Allocation
- Dynamic Power Coordination
- Digital Media Boost
- Intel Advanced Thermal Management
Smart Cache: Cache As Much As You Can
In contrast to the dual core CPUs in the Intel Pentium D 900 series for desktop PCs, the new mobile dual core processors include two independent processor units that share a single 2 MB L2 cache. Both sit on the same die, and both use the same front side bus to access the chipset, the L2 cache, and communicate with each other. Intel calls this shared 2 MB L2 cache "Smart Cache".
Smart Cache Architecture of the Core Duo processors, aka Yonah
In the Pentium D 900 desktop processors, on the other hand, each core has its own 2 MB L2 cache, with each pair (core and cache) residing on its own die, though both dies interconnect with each other using the front side bus.
Split Cache Architecture in the Pentium D 900
What advantages does the Core Duo's Smart Cache architecture on the Yonah processor enjoy when compared to split-cache variants, like those found in desktop processors such as the Pentium D 900? Well, assume for example that both CPUs are working in parallel on the same task, such as on image filtering in Photoshop. In that case, it's important for both cores to be aware of where current, valid data entries reside in the L2 cache, and to know if such entries must be loaded from the system RAM instead - a process that takes considerably longer to complete than cache access. Both cores need to make sure they're working together and not at cross purposes to get things done quickly, and make sure that core 1 won't overwrite data that core 2 has already worked on.
A shared L2 cache, in connection with a shared FSB, implements a kind of high-speed link between the cores right on the chip. In addition, this architecture/design (two cores with a single shared L2 cache) reduces the amount of FSB traffic, which in turn has a positive impact on both energy consumption and overall performance. In a split-cache design, on the other hand, information exchange between the two cores involves determining whether current valid data resides in the other L2 cache or in RAM; either of these involves time-consuming transfers across the FSB.
When used in tandem with Dynamic Cache Allocation, the number of cache misses when compared to a split-cache design should be noticeably lower, in keeping with the motto, "Cache as much as you can." In this context, Dynamic Cache Allocation means that each of the two cores always uses as much of the 2 MB L2 cache as the running applications allow. In other words, there's no fixed limit on cache allocation for either core. In addition, Intel core processors can turn off the power to unused portions of the L2 cache based on workloads in execution, thereby saving energy. This artful dodge does not affect data integrity in the L2 cache either.
- Is Faster Notebook Performance Worth Shorter Battery Life?
- Yonah: Pentium M Successor With Two Cores
- ..., Faster Front Side Bus (FSB),
- ...and Other Important Enhancements
- Dynamic Power Coordination
- Dynamic Power Coordination, Continued
- Digital Media Boost
- I've Got A Core Duo Processor LV L2400. What Have You Got?
- Models And Pricing For Core Duo And Core Solo CPUs
- Overview Of All Centrino Generations
- New Chipsets And Two Different Southbridges
- Test System Configuration Details And Comparison Systems
- Benchmarks And Settings
- Extended Benchmark Suite
- ABBYY FineReader 8
- Application Test Results
- Windows Media Encoder 9
- Results From The Multitasking Scenarios
- Office Applications: SYSmark 2004 SE
- SYSmark 2004 SE, Continued
- Battery Life: MobileMark 2005
- MobileMark 2005, Continued
- Energy Drain: Graphics Chip Or Chipset?
- Summary And Conclusions
- Summary And Conclusions, Continued