- Articles & News
- For IT Pros
- Your Opinion
Intel wouldn't be Intel if it didn't garnish the introduction of a new CPU model series with a bundle of new marketing buzzwords. In the pages that follow we'll shed light on these new terms:
In contrast to the dual core CPUs in the Intel Pentium D 900 series for desktop PCs, the new mobile dual core processors include two independent processor units that share a single 2 MB L2 cache. Both sit on the same die, and both use the same front side bus to access the chipset, the L2 cache, and communicate with each other. Intel calls this shared 2 MB L2 cache "Smart Cache".
In the Pentium D 900 desktop processors, on the other hand, each core has its own 2 MB L2 cache, with each pair (core and cache) residing on its own die, though both dies interconnect with each other using the front side bus.
What advantages does the Core Duo's Smart Cache architecture on the Yonah processor enjoy when compared to split-cache variants, like those found in desktop processors such as the Pentium D 900? Well, assume for example that both CPUs are working in parallel on the same task, such as on image filtering in Photoshop. In that case, it's important for both cores to be aware of where current, valid data entries reside in the L2 cache, and to know if such entries must be loaded from the system RAM instead - a process that takes considerably longer to complete than cache access. Both cores need to make sure they're working together and not at cross purposes to get things done quickly, and make sure that core 1 won't overwrite data that core 2 has already worked on.
A shared L2 cache, in connection with a shared FSB, implements a kind of high-speed link between the cores right on the chip. In addition, this architecture/design (two cores with a single shared L2 cache) reduces the amount of FSB traffic, which in turn has a positive impact on both energy consumption and overall performance. In a split-cache design, on the other hand, information exchange between the two cores involves determining whether current valid data resides in the other L2 cache or in RAM; either of these involves time-consuming transfers across the FSB.
When used in tandem with Dynamic Cache Allocation, the number of cache misses when compared to a split-cache design should be noticeably lower, in keeping with the motto, "Cache as much as you can." In this context, Dynamic Cache Allocation means that each of the two cores always uses as much of the 2 MB L2 cache as the running applications allow. In other words, there's no fixed limit on cache allocation for either core. In addition, Intel core processors can turn off the power to unused portions of the L2 cache based on workloads in execution, thereby saving energy. This artful dodge does not affect data integrity in the L2 cache either.