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The Force Is On Its Side: nForce2 With Dual DDR400

Full Power: NVIDIA Attacks With nForce2
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Up till now, dual-channel DDR mode has only been used by the nForce and Intel's E7500 chipset. The nForce2 is the third member of this group, and, through further optimizing as well as increasing the the clock speed up to 200 MHz (DDR400), the system performance should increase accordingly.

Dual-channel DDR operation with DDR266, DDR333 or even DDR400 works with the IGP as well as the SPP. The memory controller of course has two separate data buses for dual-channel operation and 'only' three address buses, meaning that we won't see any motherboards with 4 DIMM sockets. According to NVIDIA, dual-channel mode also works with three DIMMs.

As with the nForce, the memory interface of the nForce2 is twice as important. For one thing, the dual memory controller enables the bandwidth to double, because the interface can work with 128-bit instead of 64-bit. This means up to 6.4 GB/s with dual DDR400, 5.4 GB/s with DDR333 and 4.2 GB/s with DDR266. These are values that make the 3.2 GB/s of dual PC800 RDRAM seem quite low. Another aspect is that the graphics unit of the nForce2 IGP doesn't have its own memory, so it always has to use a portion from the main memory. Today, AGP graphics cards have between 32 and 128 MB of dedicated memory, which usually works at much higher speeds than the system memory; so, systems with integrated graphics are almost always slower than those with separate AGP graphics cards. However, NVIDIA might not be able to solve all problems of shared memory, but, with the use of dual DDR400, it offers a solution thatpromises to perform even better than the GeForce4 MX420.

Memory technology of the future: increasing the voltage from 2.5 to 2.6 or 2.65 V enables a memory clock of 200 MHz. Thanks to double data rate technology, this corresponds to a performance level that SDRAM could only achieve at 400 MHz: DDR can transfer double the amount of data per clock cycle. The nForce2 can manage two memory channels simultaneously.

It cannot be said that the bus width is simply doubled, because, as a matter of fact, both of the memory controllers cooperate in an intelligent manner. The goal is to minimize the latency (waiting cycles that occur when accessing SDRAM) through alternating use of a second memory controller. Also, StreamThru access (realtime data transfer, see details below) gets the highest priority. For example, while the first controller prepares for memory access, the read process can occur through the second controller at the same time. Theoretically, this would lead to a reduction of the latency by one half.

Moreover, NVIDIA gives the memory controllers various algorithems in order to predict and optimize memory access. This feature is called DASP (Dynamic Adaptive Speculative Preprocessor), which, according to the datasheet, has been significantly improved compared to the first nForce chipset. This remains to be confirmed by extensive testing.

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